FlintyLemming/PLFM_RADAR
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Author SHA1 Message Date
Jason eefaf94e9e Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis 
Resolves all synthesis errors across attempts 3-11, achieving clean
Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs).

radar_receiver_final.v:
- reg clk_400m -> wire; output reg -> output wire (x4)
- Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m
- Remove duplicate IBUFDS lvds_to_cmos_400m instantiation
- Remove non-existent ref_i/ref_q port connections on matched filter
- Connect adc_dco_bufg as 400MHz clock source

ad9484_interface_400m.v:
- Add adc_dco_bufg output port with BUFG instance
- Route all internal logic through buffered DCO clock

cic_decimator_4x_enhanced.v:
- Move reset_monitors handling inside else branch (fixes Vivado
  ambiguous clock error in both integrator and comb always blocks)
- Add separate comb_overflow_latched/comb_saturation_detected regs
  to eliminate multi-driven nets between integrator and comb blocks
- Remove standalone always @(posedge reset_monitors) block
- Add output_counter to async reset branch

matched_filter_processing_chain.v:
- Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION
- Add synthesis stub tying outputs to safe defaults

chirp_memory_loader_param.v:
- Replace hardcoded Windows paths with relative filenames for all
  10 $readmem default parameters

latency_buffer_2159.v:
- Split single always block into separate BRAM write (synchronous
  only) and control logic (with async reset) blocks
- Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset

xfft_32.v (NEW):
- Synthesis stub for Xilinx 32-point FFT IP core
- AXI-Stream interface with pass-through and 1-cycle latency
- Placeholder until real xfft IP is generated
 2026-03-15 17:37:59 +02:00
Jason c871281f1e Fix synthesis blockers in 9 RTL files for Vivado compatibility 
Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)
 2026-03-15 14:53:35 +02:00
Jason f5a3394f23 Add 3 missing FPGA modules with enhanced testbenches (168/168 pass) 
Implement the 3 modules identified as missing during repo audit:
- matched_filter_processing_chain: behavioral FFT-based pulse compression
- range_bin_decimator: 1024→64 bin decimation with 3 modes + start_bin
- radar_mode_controller: 4-mode beam/chirp controller

Wire radar_mode_controller into radar_receiver_final.v to drive the
previously-undriven use_long_chirp and mc_new_* signals.

Implement start_bin functionality in range_bin_decimator (was dead code
in the original interface contract — now skips N input bins before
decimation for region-of-interest selection).

Add comprehensive testbenches with Tier 1 confidence improvements:
- Golden reference co-simulation (Python FFT → hex → bin comparison)
- Saturation boundary tests (0x7FFF / 0x8000 extremes)
- Reset mid-operation recovery tests
- Valid-gap / stall handling tests
- Mode switching and counter persistence tests
- Accumulator overflow stress tests

Test counts: matched_filter 40/40, range_bin_decimator 55/55,
radar_mode_controller 73/73 — all passing with iverilog -g2001.
 2026-03-15 13:37:10 +02:00
Jason 81435f9ff9 Merge branch 'main' of https://github.com/NawfalMotii79/PLFM_RADAR 2026-03-15 06:22:27 +02:00
Jason 558f49cd4a Add 8 Verilog testbenches with full coverage (144/144 pass) 
Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).

Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.
 2026-03-15 06:14:11 +02:00
Jason 76183e2e95 Fix 6 RTL bugs in FPGA signal processing chain 
- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port

All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).
 2026-03-15 06:14:04 +02:00
NawfalMotii79 74d5a76abb Merge pull request #7 from walidb212/fix/gy85-i2c-status 
fix(firmware): propagate gy85 i2c failures
 2026-03-15 01:57:28 +00:00
NawfalMotii79 eca26f413d Merge pull request #6 from walidb212/refactor/adar-sequencing-constants 
refactor(firmware): name adar power sequencing constants
 2026-03-15 01:56:59 +00:00
NawfalMotii79 e212c806d4 Merge pull request #5 from walidb212/fix/gps-transport-status 
fix(firmware): return gps transport status
 2026-03-15 01:56:16 +00:00
NawfalMotii79 63c0aedc3b Merge pull request #8 from walidb212/fix/gui-settings-validation 
fix(gui): validate radar settings before usb send
 2026-03-15 00:52:05 +00:00
NawfalMotii79 246d088169 Update README with licensing details 
Added hardware and software licensing information to the README, detailing the CERN Open Hardware License for hardware and the MIT License for software.
 2026-03-15 00:39:23 +00:00
NawfalMotii79 eed253cab0 Add CERN Open Hardware Licence Version 2 - Permissive 
This commit adds the CERN Open Hardware Licence Version 2 - Permissive to the project, providing legal guidelines for hardware design dissemination and collaboration.
 2026-03-15 00:34:27 +00:00
wb-eugenia a4b8a144ed fix(firmware): return gps transport status 2026-03-13 19:41:45 +01:00
wb-eugenia 9bb6080a73 fix(firmware): propagate gy85 i2c failures 2026-03-13 19:38:42 +01:00
wb-eugenia b1cb897275 refactor(firmware): name adar power sequencing constants 2026-03-13 19:32:10 +01:00
wb-eugenia 2d62d4320c fix(gui): validate radar settings before usb send 2026-03-13 19:28:35 +01:00
NawfalMotii79 7510e31c20 Update image path for AERIS-10 Radar System 2026-03-11 02:04:42 +00:00
NawfalMotii79 19bcbba835 Add files via upload 2026-03-11 02:02:03 +00:00
NawfalMotii79 4781ab1001 Include radar system image in README 
Add image of AERIS-10 Radar System to README
 2026-03-11 02:01:34 +00:00
NawfalMotii79 ea3319353b Add files via upload 2026-03-10 23:39:49 +00:00
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NawfalMotii79 11089dfacd Update GUI_V6_Demo.py 2026-03-10 01:55:47 +00:00
NawfalMotii79 90bab6bd64 Create GUI_V6_Demo.py 2026-03-10 01:43:19 +00:00
NawfalMotii79 a7e55c752f Create usb_packet_analyzer.v 2026-03-10 01:36:04 +00:00
NawfalMotii79 220f2e0d0b Create radar_system_tb.v 2026-03-10 01:35:26 +00:00
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NawfalMotii79 0eb2d9726d Update GUI_versions.txt 2026-03-10 01:27:05 +00:00
NawfalMotii79 43ff85e331 Update and rename GUI_V6 to GUI_V6.py 2026-03-10 01:26:00 +00:00
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NawfalMotii79 4cb53454ec Update README.md 2026-03-09 01:30:03 +00:00
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