6 Commits

Author	SHA1	Message	Date
Jason	f154edbd20	Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001 ... - Regenerate all 10 chirp .mem files with correct AERIS-10 parameters (gen_chirp_mem.py: phase = pi*chirp_rate*t^2, 4 segments x 1024) - Add gen_chirp_mem.py script for reproducible .mem generation - Add tb_usb_data_interface.v testbench (39/39 PASS) - Convert radar_system_tb.v from SystemVerilog to Verilog-2001: replace $sin() with LUT, inline integer decl, SVA with procedural checks - All testbenches pass: integration 10/10, MF 3/3, multi-seg 32/32, DDC 4/4, Doppler 14/14, USB 39/39, .mem validation 56/56 - Vivado timing closure confirmed: WNS=+0.021ns on xc7a100t-csg324-1	2026-03-16 19:53:40 +02:00
Jason	2db32af1d0	Add .mem file validator: verify FFT twiddle + chirp .mem files against radar parameters (55/56 PASS)	2026-03-16 19:02:45 +02:00
Jason	e76925391c	Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS) ... RTL fix: matched_filter_multi_segment.v ST_WAIT_FFT now waits for processing chain to complete ALL 1024 outputs and return to IDLE before advancing to next segment. Previously, it transitioned on the first fft_pc_valid edge, causing the chain to still be outputting while multi-seg started collecting data for the next segment. This broke the handshake and caused permanent deadlock after segment 0. Also fixes forward reference of sample_addr_from_chain in radar_receiver_final.v (declaration moved before first use). New files: - tb/tb_radar_receiver_final.v: P0 integration test for full RX pipeline (ADC->DDC->MF->range_bin_decimator->doppler), 10 checks - tb/ad9484_interface_400m_stub.v: behavioral ADC stub for iverilog All existing tests still pass: multi-seg 32/32, MF co-sim 3/3, Doppler co-sim 14/14.	2026-03-16 18:51:08 +02:00
Jason	17731dd482	Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites ... RTL bug fixes: - doppler_processor.v: Add S_PRE_READ state to prime BRAM pipeline, restructure S_LOAD_FFT with sub-counter staging, fix BRAM address off-by-one (read_doppler_index <= fft_sample_counter + 2, was +1). All 3 Doppler co-sim scenarios now achieve BIT-PERFECT match (correlation=1.0, energy=1.0). - matched_filter_multi_segment.v: Move buffer_write_ptr >= SEGMENT_ADVANCE check outside if(ddc_valid) block to prevent FSM deadlock. 32/32 tests PASS. New co-simulation infrastructure: - Doppler co-sim: tb_doppler_cosim.v (14/14 structural checks), gen_doppler_golden.py (3 scenarios: stationary/moving/two_targets), compare_doppler.py (bit-perfect thresholds) - Multi-segment co-sim: tb_multiseg_cosim.v (32/32), gen_multiseg_golden.py with short and long test vector suites	2026-03-16 18:09:26 +02:00
Jason	e506a80db5	Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)	2026-03-16 16:23:01 +02:00
Jason	baa24fd01e	Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation ... Bit-accurate Python model (fpga_model.py) mirrors full DDC RTL chain: NCO -> mixer -> CIC -> FIR with exact fixed-point arithmetic matching RTL DSP48E1 pipeline behavior including CREG=1 delay on CIC int_0. Synthetic radar scene generator (radar_scene.py) produces ADC test vectors for 5 scenarios: DC, single target (500m), multi-target (5), noise-only, and 1 MHz sine wave. DDC co-sim testbench (tb_ddc_cosim.v) feeds hex vectors through RTL DDC and exports baseband I/Q to CSV. All 5 scenarios compile and run with Icarus Verilog (iverilog -g2001 -DSIMULATION). Comparison framework (compare.py) validates Python vs RTL using statistical metrics (RMS ratio, DC offset, peak ratio) rather than exact sample match due to RTL LFSR phase dithering. Results: 5/5 PASS.	2026-03-16 16:01:40 +02:00