e76925391c
Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)
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RTL fix: matched_filter_multi_segment.v ST_WAIT_FFT now waits for
processing chain to complete ALL 1024 outputs and return to IDLE
before advancing to next segment. Previously, it transitioned on the
first fft_pc_valid edge, causing the chain to still be outputting
while multi-seg started collecting data for the next segment. This
broke the handshake and caused permanent deadlock after segment 0.
Also fixes forward reference of sample_addr_from_chain in
radar_receiver_final.v (declaration moved before first use).
New files:
- tb/tb_radar_receiver_final.v: P0 integration test for full RX
pipeline (ADC->DDC->MF->range_bin_decimator->doppler), 10 checks
- tb/ad9484_interface_400m_stub.v: behavioral ADC stub for iverilog
All existing tests still pass: multi-seg 32/32, MF co-sim 3/3,
Doppler co-sim 14/14.
2026-03-16 18:51:08 +02:00
eefaf94e9e
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
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Resolves all synthesis errors across attempts 3-11, achieving clean
Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs).
radar_receiver_final.v:
- reg clk_400m -> wire; output reg -> output wire (x4)
- Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m
- Remove duplicate IBUFDS lvds_to_cmos_400m instantiation
- Remove non-existent ref_i/ref_q port connections on matched filter
- Connect adc_dco_bufg as 400MHz clock source
ad9484_interface_400m.v:
- Add adc_dco_bufg output port with BUFG instance
- Route all internal logic through buffered DCO clock
cic_decimator_4x_enhanced.v:
- Move reset_monitors handling inside else branch (fixes Vivado
ambiguous clock error in both integrator and comb always blocks)
- Add separate comb_overflow_latched/comb_saturation_detected regs
to eliminate multi-driven nets between integrator and comb blocks
- Remove standalone always @(posedge reset_monitors) block
- Add output_counter to async reset branch
matched_filter_processing_chain.v:
- Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION
- Add synthesis stub tying outputs to safe defaults
chirp_memory_loader_param.v:
- Replace hardcoded Windows paths with relative filenames for all
10 $readmem default parameters
latency_buffer_2159.v:
- Split single always block into separate BRAM write (synchronous
only) and control logic (with async reset) blocks
- Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset
xfft_32.v (NEW):
- Synthesis stub for Xilinx 32-point FFT IP core
- AXI-Stream interface with pass-through and 1-cycle latency
- Placeholder until real xfft IP is generated
2026-03-15 17:37:59 +02:00
c871281f1e
Fix synthesis blockers in 9 RTL files for Vivado compatibility
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Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)
Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)
2026-03-15 14:53:35 +02:00
f5a3394f23
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
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Implement the 3 modules identified as missing during repo audit:
- matched_filter_processing_chain: behavioral FFT-based pulse compression
- range_bin_decimator: 1024→64 bin decimation with 3 modes + start_bin
- radar_mode_controller: 4-mode beam/chirp controller
Wire radar_mode_controller into radar_receiver_final.v to drive the
previously-undriven use_long_chirp and mc_new_* signals.
Implement start_bin functionality in range_bin_decimator (was dead code
in the original interface contract — now skips N input bins before
decimation for region-of-interest selection).
Add comprehensive testbenches with Tier 1 confidence improvements:
- Golden reference co-simulation (Python FFT → hex → bin comparison)
- Saturation boundary tests (0x7FFF / 0x8000 extremes)
- Reset mid-operation recovery tests
- Valid-gap / stall handling tests
- Mode switching and counter persistence tests
- Accumulator overflow stress tests
Test counts: matched_filter 40/40, range_bin_decimator 55/55,
radar_mode_controller 73/73 — all passing with iverilog -g2001.
2026-03-15 13:37:10 +02:00
76183e2e95
Fix 6 RTL bugs in FPGA signal processing chain
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- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port
All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).
2026-03-15 06:14:04 +02:00
5fbe97fa5f
Add files via upload
2026-03-09 00:17:39 +00:00
Jason
NawfalMotii79