19284ac277
Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21
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Build 21 Vivado results extracted and documented:
- WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met)
- 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%)
- Total power: 0.732 W
- Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected
- TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug)
- Updated release-notes.html, implementation-log.html, reports.html
2026-03-20 02:21:33 +02:00
05efe692ad
Add Build 21 TCL script for FFT opts + E2E RTL fixes Vivado build
2026-03-20 01:48:51 +02:00
c6103b37de
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
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MMCM (Gap 7):
- Add adc_clk_mmcm.v: MMCME2_ADV wrapper (VCO=800MHz, CLKOUT0=400MHz)
- Modify ad9484_interface_400m.v: replace BUFG with MMCM path, gate reset on mmcm_locked
- Add adc_clk_mmcm.xdc: CDC false paths for clk_mmcm_out0 <-> clk_100m
XDC Fix (Build 19 WNS=-0.011 root cause):
- Remove conflicting create_generated_clock -name clk_400m_mmcm
- Replace all clk_400m_mmcm references with Vivado auto-generated clk_mmcm_out0
- CDC false paths now correctly apply to actual timing paths
CIC CREG Pipeline (Build 18 critical path fix):
- Explicit DSP48E1 for comb[0] with CREG=1/AREG=1/BREG=1/PREG=1
- Absorbs integrator_sampled_comb fabric FDRE into DSP48 C-port register
- Eliminates 0.643ns fabric->DSP routing delay (Build 18 tightest path)
- +1 cycle comb latency via data_valid_comb_0_out pipeline
- Move shared register declarations above ifndef SIMULATION (iverilog fix)
- Update golden data for +1 cycle CIC pipeline shift
Build scripts: build19_mmcm.tcl, build20_mmcm_creg.tcl
Regression: 18/18 FPGA pass, 20/20 MCU pass
Build 20 launched on remote Vivado (pending results)
2026-03-19 22:59:46 +02:00
3b7afba9d9
Add Build 18 production script with report_exceptions fix for Vivado 2025.2
2026-03-19 20:40:32 +02:00
4e3c20066b
Add Build 17 production build script with full 15-point analysis checklist
2026-03-19 17:07:02 +02:00
8ca6d992cb
Update ILA probe script references from Build 13 to Build 16
2026-03-19 17:01:12 +02:00
967ce179eb
Add TE0713/TE0701 alternate dev target for in-stock SoM path
2026-03-18 15:02:09 +02:00
0ae7b40ff0
Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
2026-03-18 03:57:26 +02:00
12e63b750c
Fix ILA probe insertion script: deferred core creation, exact-path net resolution, Vivado 2025.2 MU_CNT minimum
2026-03-18 02:26:09 +02:00
f6877aab64
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
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- Rename latency_buffer_2159 -> latency_buffer (module + file + all refs)
- Add CDC waivers for 5 verified false-positive criticals to XDC
- Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains)
- Add FPGA programming script (7-step flow with DONE pin verification)
- Add ILA capture script (4 scenarios + health check, CSV export)
- Add debug_ila.xdc with MARK_DEBUG fallback attributes
- Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match
2026-03-18 01:28:42 +02:00
5fd632bc47
Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator
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CDC fixes across 6 RTL files based on post-implementation report_cdc analysis:
- P0: sync stm32_mixers_enable and new_chirp_pulse to clk_120m via toggle CDC
in radar_transmitter, add ft601 reset synchronizer and USB holding
registers with proper edge detection in usb_data_interface
- P1: add ASYNC_REG to edge_detector, convert new_chirp_frame to toggle CDC,
fix USB valid edge detect to use fully-synced signal
- P2: register Gray encoding in cdc_adc_to_processing source domain, sync
ft601_txe and stm32_mixers_enable for status_reg in radar_system_top
- Safety: add in_bin_count overflow guard in range_bin_decimator to prevent
downstream BRAM corruption
All 13 regression test suites pass (159 individual tests).
2026-03-17 13:48:47 +02:00
Jason