4 Commits

Author	SHA1	Message	Date
Jason	c983a3c705	Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG ... Phase 0+ timing optimization (attempts #13-22 + implementation): NCO (nco_400m_enhanced.v): - 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX - DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain) - Registered phase_inc_dithered to break cascaded 32-bit add path DDC (ddc_400m.v): - Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1) - CEP=1, RSTP=!reset_n for proper pipeline control - 3-stage dsp_valid_pipe for PREG=1 latency - Behavioral sim model under ifdef SIMULATION for Icarus compatibility CIC (cic_decimator_4x_enhanced.v): - 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28 - Removed integrator/comb saturation (CIC uses wrapping arithmetic by design) - Pipelined output saturation comparison CDC/ASYNC_REG: - ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v, radar_system_top.v, usb_data_interface.v) - Sync reset in generate blocks (cdc_modules.v) Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints, 850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t. All testbenches pass: 241/244 (3 known stub failures).	2026-03-16 01:02:07 +02:00
Jason	ffed7c1623	Fix CDC timing violations: add synchronizers for all inter-clock crossings ... Resolve all 4 inter-clock timing violations found in Vivado synthesis attempt #11 (WNS was -2.552 ns). Changes: - Add reset synchronizer for clk_120m_dac domain (2-FF chain) - Add Gray-code CDC for chirp_counter (6-bit, 120MHz->100MHz) - Add single-bit CDC for new_chirp_frame (3-stage, 120MHz->100MHz) - Add 2-stage input synchronizers for valid signals in USB module (clk_100m->ft601_clk_in) with data capture on rising edge - Fix ft601_clk_out multi-driven net (removed duplicate assignment) - Update XDC: set_max_delay -datapath_only for CDC, false_path for reset Result: Vivado attempt #12 passes with 0 errors, 0 timing violations, and 'All user specified timing constraints are met.' (WNS +0.983 ns)	2026-03-15 17:58:14 +02:00
Jason	76183e2e95	Fix 6 RTL bugs in FPGA signal processing chain ... - nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error) - ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance) - plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical) - radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver - radar_receiver_final.v: Promote chirp_counter to input port All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).	2026-03-15 06:14:04 +02:00
NawfalMotii79	45ad19184c	Add files via upload	2026-03-10 01:31:50 +00:00