3 Commits

Author	SHA1	Message	Date
Jason	94ffdb8f77	Add Phase 0 Vivado-style lint to regression runner, update golden data ... Adds two-layer lint pass (iverilog -Wall + custom static checks) that catches part-select OOB errors and case-without-default warnings before pushing to remote Vivado. Catches the exact Synth 8-524 class error that broke Build 18 initial attempt. Lint errors abort regression; warnings are advisory. Regenerated golden data for BRAM-migrated matched filter.	2026-03-19 21:19:07 +02:00
Jason	ed6f79c6d3	FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache ... FIR: Add coeff_reg/mult_reg pipeline stages to fix 68 DPIP-1 + 35 DPOP-2 DRC warnings. Valid pipeline widened 7→9 bits (+2 cycle latency). Matched filter: Migrate input_buffer_i/q from register arrays to BRAM (~33K FF savings). Overlap-save uses register cache captured during ST_PROCESSING to avoid BRAM read/write conflicts during overlap copy. New ST_OVERLAP_COPY state writes cached tail samples back sequentially. Both changes pass 18/18 FPGA regression. Golden data regenerated for +2 FIR latency baseline.	2026-03-19 20:39:01 +02:00
Jason	47606a4459	Rewrite integration testbench with golden self-reference comparison + physics bounds checks ... Replace smoke-test integration TB (10 liveness checks) with golden comparison architecture (18 checks). Two compile-time modes: - GOLDEN_GENERATE: dumps 2048 Doppler outputs to golden_doppler.mem - Default: loads golden, compares within ±2 LSB tolerance per channel New checks: G1 golden comparison (2048/2048 exact match verified), B1a/b DDC energy bounds, B2a/b Doppler per-bin energy, B3 exact count, B4 full 64x32 bin coverage, B5 no duplicate indices. Fault injection verified: zeroing FIR coeff[15] causes 2048/2048 golden mismatches (max err 1234/1443 LSB), confirming regression guard.	2026-03-17 20:56:28 +02:00