3 Commits

Author	SHA1	Message	Date
Jason	fd6094ee9e	Fix P0/P1 RTL bugs found during pre-hardware audit ... P0-1: nco_400m_enhanced.v — DSP48E1 OPMODE corrected from PCIN to P feedback (was routing stale cascade data into accumulator) P0-2: radar_receiver_final.v — removed same-clock CDC that corrupted ADC data path between ad9484_interface and DDC P1-5: fir_lowpass.v — fixed zero replication count in coefficient symmetric extension ({0{1'b0}} is empty, now uses explicit 0) Also updates .gitignore to exclude debug/scratch artifacts. All 30+ testbenches pass (unit, co-sim, integration).	2026-03-16 22:24:06 +02:00
Jason	00fbab6c9d	Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations) ... Complete FPGA timing closure across all clock domains after 9 iterative Vivado builds. WNS improved from -48.325ns to +0.018ns (107,886 endpoints). RTL fixes for 400 MHz timing: - NCO: 6-stage pipeline with DSP48E1 phase accumulator, registered LUT index (Fix D splits address decode from ROM read), distributed RAM - CIC: explicit DSP48E1 PCOUT->PCIN cascade for 5 integrator stages, CREG=1 on integrator_0 to eliminate fabric->DSP setup violation - DDC: 400 MHz reset synchronizer (async-assert/sync-deassert), active-high reset register for DSP48E1 RST ports, posedge output stage - FIR: 5-stage binary adder tree pipeline (7-cycle latency) - FFT: 5-cycle butterfly pipeline with registered twiddle index, XPM_MEMORY_TDPRAM for data storage - XDC: CDC false paths, async reset false paths, CIC comb multicycle paths Final Build 9 timing (all MET): adc_dco_p (400 MHz): WNS = +0.278ns clk_100m (100 MHz): WNS = +0.018ns clk_120m_dac (120 MHz): WNS = +0.992ns ft601_clk_in (100 MHz): WNS = +5.229ns Cross-domain (adc_dco_p->clk_100m): WNS = +7.105ns	2026-03-16 15:02:35 +02:00
NawfalMotii79	5fbe97fa5f	Add files via upload	2026-03-09 00:17:39 +00:00