5 Commits

Author	SHA1	Message	Date
Jason	2106e24952	fix: enforce strict ruff lint (17 rule sets) across entire repo ... - Expand ruff config from E/F to 17 rule sets (B, RUF, SIM, PIE, T20, ARG, ERA, A, BLE, RET, ISC, TCH, UP, C4, PERF) - Fix 907 lint errors across all Python files (GUI, FPGA cosim, schematics scripts, simulations, utilities, tools) - Replace all blind except-Exception with specific exception types - Remove commented-out dead code (ERA001) from cosim/simulation files - Modernize typing: deprecated typing.List/Dict/Tuple to builtins - Fix unused args/loop vars, ambiguous unicode, perf anti-patterns - Delete legacy GUI files V1-V4 - Add V7 test suite, requirements files - All CI jobs pass: ruff (0 errors), py_compile, pytest (92/92), MCU tests (20/20), FPGA regression (25/25)	2026-04-12 14:21:03 +05:45
Jason	11aa590cf2	fix: full-repo ruff lint cleanup and CI migration to uv ... Resolve all 374 ruff errors across 36 Python files (E501, E702, E722, E741, F821, F841, invalid-syntax) bringing `ruff check .` to zero errors repo-wide with line-length=100. Rewrite CI workflow to use uv for dependency management, whole-repo `ruff check .`, py_compile syntax gate, and merged python-tests job. Add pyproject.toml with ruff config and uv dependency groups. CI structure proposed by hcm444.	2026-04-09 02:05:34 +03:00
NawfalMotii79	c7fa099293	Add files via upload	2026-04-02 01:04:55 +01:00
NawfalMotii79	81bf4cabbb	Delete 8_Utils directory	2026-04-02 01:03:40 +01:00
NawfalMotii79	8974a38ff6	Add files via upload	2026-03-09 00:11:57 +00:00