9b786eb33f
Add FMC-path FT601 XDC for TE0713+TE0701+UMFT601X-B pin mapping
...
Maps all 47 FT601 signals through FMC LPC J10 to correct FPGA pins:
- DATA[31:0] + D_CLK: Bank 15 (LA17-LA33)
- BE_N[3:0], control, status: Bank 16 (LA00-LA15)
Both banks share VIOTB rail — set to 3.3V for LVCMOS33.
Includes timing constraints and RTL adaptation notes.
2026-03-19 16:20:56 +02:00
f16d9524e5
Add board-day worksheet and cross-link bring-up docs
2026-03-19 15:25:23 +02:00
0009a74a49
Expand pre-hardware bring-up readiness docs
2026-03-19 14:57:56 +02:00
e62f3cd950
Port validated Build 16 XDC cleanup and sync docs
2026-03-19 14:34:26 +02:00
2763b4be91
Fix CFAR blocking assignment (= to <=) in clocked block, add Build 15 analysis report
...
CFAR magnitude computation in radar_system_top.v used blocking assignment (=)
inside posedge-clocked always block, creating sim/synth mismatch risk. Changed
to non-blocking (<=). Threshold check now reads previous cycle's magnitude,
which is correct sequential behavior. Regression: 15/15 quick + system TB pass.
Build 15 analysis written to 10_docs/reports/ (not tracked — gitignored).
2026-03-19 13:22:15 +02:00
3fa26c9e4c
Wire matched filter range profile to USB, replacing Doppler placeholder
2026-03-19 12:33:40 +02:00
f4ff2715ca
Fix matched filter golden test paths (40/40 pass, was 37/40)
2026-03-19 12:20:37 +02:00
463ebef554
CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
...
- cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and
data_valid_comb_pipe pipeline stages between integrator sampling and
comb computation to break the critical path (matches remote 40cda0f)
- radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard
with pass-through assigns for iverilog compatibility
- radar_system_tb.v: Convert generate_radar_echo function to task and
move sin_lut declaration before task (iverilog declaration-order fix),
add modular index clamping to prevent LUT out-of-bounds
- run_regression.sh: Automated regression runner for all 18 FPGA
testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail
- .gitignore: Exclude *.vvp, *.vcd simulation artifacts
2026-03-19 11:31:46 +02:00
c466021bb6
Fix bugs B12-B17 (PA cal loop, ADC buffer, DIAG_SECTION args, htim3 init, stale annotations) with regression tests
...
B12: PA IDQ calibration loop condition inverted (< 0.2 -> > 0.2) for both DAC1/DAC2
B13: DAC2 ADC buffer mismatch — reads from hadc2 now correctly stored to adc2_readings
B14: DIAG_SECTION macro call sites changed from 2-arg to 1-arg form (4 sites)
B15: htim3 definition + MX_TIM3_Init() added (PWM mode, CH2+CH3, Period=999)
B16: Removed stale NO-OP annotation on TriggerTimedSync (already fixed in Bug #3 )
B17: Updated stale GPIO-only warnings to reflect TIM3 PWM implementation (Bug #5 )
All 15 tests pass (11 original + 4 new for B12-B15).
2026-03-19 11:04:53 +02:00
49c9aa28ad
Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)
...
Bug #11 : platform_noos_stm32.c used HAL_SPI_Transmit instead of
HAL_SPI_TransmitReceive — reads returned garbage. Changed to in-place
full-duplex. Dead code (never called), fixed per audit recommendation.
Test added: test_bug11_platform_spi_transmit_only.c. Mock infrastructure
updated with SPI spy types. All 11 firmware tests pass.
FPGA B2: Migrated long_chirp_lut[0:3599] from ~700 lines of hardcoded
assignments to BRAM with (* ram_style = "block" *) attribute and
$readmemh("long_chirp_lut.mem"). Added sync-only read block for proper
BRAM inference. 1-cycle read latency introduced. short_chirp_lut left
as distributed RAM (60 entries, too small for BRAM).
FPGA B3: Added BREG (window_val_reg) and MREG (mult_i_raw/mult_q_raw)
pipeline stages to doppler_processor.v. Eliminates DPIP-1 and DPOP-2
DRC warnings. S_LOAD_FFT retimed: fft_input_valid starts at sub=2,
+1 cycle total latency. BREG primed in S_PRE_READ at no extra cost.
Both FPGA files compile clean with Icarus Verilog.
2026-03-19 10:31:16 +02:00
3b32f67087
Fix SPI bugs #9 (NULL platform_ops) and #10 (missing CS toggle), widen chip_select to uint16_t
...
Bug #9 : Both TX and RX SPI init params had platform_ops = NULL, causing
adf4382_init() -> no_os_spi_init() to fail with -EINVAL. Fixed by setting
platform_ops = &stm32_spi_ops and passing stm32_spi_extra with correct CS
port/pin for each device.
Bug #10 : stm32_spi_write_and_read() never toggled chip select. Since TX
and RX ADF4382A share SPI4, every register write hit both PLLs. Rewrote
stm32_spi.c to assert CS LOW before transfer and deassert HIGH after,
using stm32_spi_extra metadata. Backward-compatible: legacy callers
(e.g., AD9523) with cs_port=NULL skip CS management.
Also widened chip_select from uint8_t to uint16_t in no_os_spi.h since
STM32 GPIO_PIN_xx values (e.g., GPIO_PIN_14=0x4000) overflow uint8_t.
10/10 tests pass (8 original + 2 new regression tests).
2026-03-19 10:00:05 +02:00
397969348e
Fix all 8 firmware bugs with regression tests
...
Bugs fixed in adf4382a_manager.c:
- Bug #1 : Move initialized=true before sync setup, propagate sync failure
- Bug #3 : Implement TriggerTimedSync with sw_sync pulse (was no-op)
- Bug #5 : Replace GPIO-only placeholder with TIM3 PWM for DELADJ
- Bug #7 : Correct GPIOG pin definitions to match CubeMX (pins 6-15)
Bugs fixed in main.cpp:
- Bug #2 : Remove pre-reset ad9523_setup() call (keep only post-reset)
- Bug #4 : Move init error check before phase shift calls
- Bug #6 : Fix timer variable (last_check -> last_check1) in temp block
- Bug #8 : Uncomment uart_print/uart_println debug helpers
Test harness updates:
- All 8 tests rewritten to assert correct post-fix behavior
- Added TIM PWM mock (SPY_TIM_PWM_START/STOP/SET_COMPARE)
- Added mock_adf4382_set_timed_sync_retval for failure injection
- Updated shims and Makefile for new test dependencies
- All 8 tests pass: make clean && make test -> 8/8 passed
2026-03-19 09:42:59 +02:00
b93ee04592
Add .gitignore for test build artifacts, remove committed binaries and .o files
2026-03-19 09:28:48 +02:00
28a66889ad
Add MCU firmware test harness with 8 bug-confirming tests
...
Complete test infrastructure for the observe-before-fix methodology:
- stm32_hal_mock: HAL stub types + spy/recording ring buffer (512 entries)
- ad_driver_mock: ADF4382/AD9523 mock drivers with configurable returns
- 9 shim headers redirecting real #includes to mock types
- Makefile with individual (test_bug1..8) and aggregate (test) targets
All 8 tests pass, confirming:
#1 Timed sync init ordering (SetupTimedSync before initialized=true)
#2 AD9523 double setup (first call before reset release)
#3 TriggerTimedSync no-op (prints messages, no HW action)
#4 Phase shift before init error check
#5 SetFinePhaseShift GPIO-only placeholder (no PWM)
#6 Timer variable collision (last_check vs last_check1)
#7 GPIO pin mapping conflict (manager.h vs CubeMX main.h)
#8 uart_print/uart_println commented out
2026-03-19 09:28:19 +02:00
fda8aab7a2
Add DIAG instrumentation to beamformer, PA, USB, and remaining main.cpp subsystems
...
Completes the observe-before-fix instrumentation pass across all critical
firmware subsystems:
- ADAR1000_Manager.cpp: 99 DIAG calls covering power-up/down, TX/RX mode
switching, ADTR1107 init sequence, SPI transfers, ADC reads (with 100ms
timeout guard on unbounded busy-wait), and scratchpad verification.
- DA5578.c: 21 DIAG calls on init, reset, channel writes, clear pin
activation, and I2C error paths.
- ADS7830.c: DIAG on init (with test-read verification) and I2C
transmit/receive error logging in single-ended and differential reads.
- USBHandler.cpp: DIAG on state transitions, start flag detection,
settings data accumulation, and SET/END marker parsing.
- main.cpp remaining sections: CDC_Receive_FS callback, systemPowerUp/Down
sequences, executeChirpSequence (entry-only, timing-critical path),
runRadarPulseSequence (beam position + stepper logging), checkSystemHealth
(per-subsystem error logging with GPIO reads), attemptErrorRecovery,
Emergency_Stop, handleSystemError, PA IDQ calibration loops (DAC/ADC init,
per-channel initial readings, calibration iterations with final values),
TMP37 ADC3 init, error handler init, and GUI status send.
No behavioral changes. All logging is compile-time removable via DIAG_DISABLE.
2026-03-19 08:57:58 +02:00
bf912067cc
Add bring-up diagnostic instrumentation to clocking/LO subsystem and main init
...
Observe-before-fix instrumentation for bench bring-up: adds timestamped
DIAG logging to the AD9523 clock config, ADF4382A LO manager, power
sequencing, lock monitoring, temperature monitoring, and safe-mode entry.
Annotates known bugs (double ad9523_setup call, timed-sync init ordering,
TriggerTimedSync no-op, phase-shift before init-check, last_check timer
collision) without changing any runtime behavior.
2026-03-19 08:32:25 +02:00
576fe71150
add contact info
...
Added contact details for collaboration.
2026-03-19 02:41:57 +00:00
b17e29e810
Add files via upload
2026-03-19 01:21:46 +00:00
b33a9bcd37
Add files via upload
2026-03-19 01:15:52 +00:00
ef0650b143
Add files via upload
2026-03-19 01:11:32 +00:00
23672d6495
Add files via upload
2026-03-19 01:09:00 +00:00
63abfaaa48
Add files via upload
2026-03-19 01:02:28 +00:00
1231c7cc94
Add files via upload
2026-03-19 00:47:41 +00:00
b8d912658b
Delete 2_Functional Diagram & Interconnection Matrices/Functional_Diagram.dwg
...
This file is the diagram of a Passive RADAR that I'm designing....nothing to do here
2026-03-18 23:31:18 +00:00
981bd271fa
Document repository file placement policy for generated artifacts
2026-03-18 22:08:57 +02:00
bb7a7390c3
Clean gitignore after root artifact reorganization
2026-03-18 22:08:02 +02:00
b879aefe6d
Ignore local cleanup artifacts and generated report directories
2026-03-18 22:04:44 +02:00
3755ee6302
Publish Simulation Report v2 aligned to current FPGA baseline
2026-03-18 21:51:08 +02:00
5710f7a83e
Annotate report currency status and flag legacy simulation PDF
2026-03-18 21:46:52 +02:00
cad804c347
Add release notes page keyed to major bring-up commits
2026-03-18 21:41:56 +02:00
94eed1e933
Expand GitHub Pages into full engineering documentation site
2026-03-18 21:40:44 +02:00
fcdd2708bb
Add GitHub Pages docs site for antenna and simulation reports
2026-03-18 21:34:26 +02:00
967ce179eb
Add TE0713/TE0701 alternate dev target for in-stock SoM path
2026-03-18 15:02:09 +02:00
25a739df07
Merge branch 'NawfalMotii79:main' into main
2026-03-18 13:25:26 +02:00
eafa6c7555
removed a short detected by @Mamenace
2026-03-18 02:36:02 +00:00
2453b16975
Add prepeg
2026-03-18 02:33:34 +00:00
0ae7b40ff0
Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
2026-03-18 03:57:26 +02:00
12e63b750c
Fix ILA probe insertion script: deferred core creation, exact-path net resolution, Vivado 2025.2 MU_CNT minimum
2026-03-18 02:26:09 +02:00
f6877aab64
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
...
- Rename latency_buffer_2159 -> latency_buffer (module + file + all refs)
- Add CDC waivers for 5 verified false-positive criticals to XDC
- Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains)
- Add FPGA programming script (7-step flow with DONE pin verification)
- Add ILA capture script (4 scenarios + health check, CSV export)
- Add debug_ila.xdc with MARK_DEBUG fallback attributes
- Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match
2026-03-18 01:28:42 +02:00
254c0e6f03
Improve timing margins with targeted datapath register tuning
...
Reduce routing pressure on CIC/NCO critical paths and move Doppler BRAM read-address registers to sync-reset datapath logic so Build 13 closes with stronger setup/hold slack while preserving functional behavior.
2026-03-17 23:51:04 +02:00
36ad15247c
Split fft_engine FSM: async reset for control, sync reset for DSP/BRAM datapath (Build 11)
...
Split monolithic always block into two:
- Block 1 (async reset): FSM state, counters, output interface
(dout_re/im, dout_valid, done) — deterministic startup
- Block 2 (sync reset): DSP/BRAM pipeline registers (rd_b_re/im,
rd_tw_cos/sin, bf_prod_re/im, rd_a_re/im, bf_t_re/im, rd_tw_idx,
rd_addr_even/odd, rd_inverse) — enables hard block absorption
Also convert output pipeline (out_pipe_valid/inverse) to sync reset.
Expected synthesis impact:
- DSP48E1 AREG/BREG absorption for butterfly multiply inputs
- DSP48E1 PREG absorption for multiply outputs (bf_prod_re/im)
- BRAM output register absorption for rd_a_re/im
- Eliminate ~300 DPIR-1 methodology warnings per FFT instance
- Resolve DPOP-2 (PREG=0), RBOR-1 (BRAM DOA), REQP-1839/1840
13/13 regression suites pass. Integration golden: 2048/2048 exact match.
2026-03-17 21:40:09 +02:00
d8a8532097
Convert CIC comb + FIR delay_line to sync reset for DSP48 absorption (Build 10)
...
CIC: async→sync reset on decimation control, valid pipeline, and comb
section. Added (* use_dsp = "yes" *) on comb[] to force DSP48E1
absorption of 28-bit subtracts (was 7-deep CARRY4, Build 9 critical
path at WNS +0.128ns). Targets ~10 additional DSP48E1s.
FIR: async→sync reset on delay_line block, enabling DSP48E1 AREG/BREG
absorption. Targets elimination of ~2,522 DPIR-1 methodology warnings.
13/13 regression suites pass. Integration golden: 2048/2048 exact match.
2026-03-17 20:56:42 +02:00
47606a4459
Rewrite integration testbench with golden self-reference comparison + physics bounds checks
...
Replace smoke-test integration TB (10 liveness checks) with golden
comparison architecture (18 checks). Two compile-time modes:
- GOLDEN_GENERATE: dumps 2048 Doppler outputs to golden_doppler.mem
- Default: loads golden, compares within ±2 LSB tolerance per channel
New checks: G1 golden comparison (2048/2048 exact match verified),
B1a/b DDC energy bounds, B2a/b Doppler per-bin energy, B3 exact count,
B4 full 64x32 bin coverage, B5 no duplicate indices.
Fault injection verified: zeroing FIR coeff[15] causes 2048/2048
golden mismatches (max err 1234/1443 LSB), confirming regression guard.
2026-03-17 20:56:28 +02:00
1558f17d05
Convert async→sync reset on DSP/BRAM datapath registers for timing closure
...
P1-CRITICAL: doppler_processor.v — split FSM into control (async reset)
and BRAM/DSP datapath (sync reset) blocks. Fixes REQP-1839/1840 BRAM
address register corruption risk; enables DSP48 absorption of window
multipliers (mult_i/q).
P1-CRITICAL: frequency_matched_filter.v — convert all 4 pipeline stages
(input capture, multiply, add, saturate) from async to sync reset.
Enables DSP48E1 absorption of complex multiplier registers.
P1-HIGH: fir_lowpass.v — convert adder tree (L0-L4), output stage, and
valid pipeline from async to sync reset. Fixes 856 DPOR-1 warnings
(428 per FIR instance × 2 I/Q channels), enabling DSP48 absorption
of the entire pipelined adder tree.
Expected impact: eliminate ~1000 DRC warnings, improve WNS from +0.019ns
by enabling Vivado to absorb hundreds of registers into DSP48E1/BRAM
hard blocks. Full regression: 13/13 test suites pass (257+ assertions).
2026-03-17 20:11:13 +02:00
fcf3999e39
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
...
Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source
and destination clock domains use correctly-synchronized resets. Previously
cdc_chirp_counter's destination-side sync chain (100MHz) was reset by
sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings.
RTL changes:
- cdc_modules.v: split reset port, source logic uses src_reset_n,
destination sync chains + output logic use dst_reset_n
- radar_system_top.v: cdc_chirp_counter gets proper per-domain resets
- ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst)
- formal/fv_cdc_adc.v: updated wrapper for new port interface
Build 7 fixes (previously untouched):
- radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync
- latency_buffer_2159.v: BRAM read registration
- constraints: ft601 IOB -quiet fix
- tb_latency_buffer.v: updated for BRAM changes
Testbench hardening (tb_cdc_modules.v, +31 new assertions):
- A5-A7: split-domain reset tests (staggered deassertion, independent
dst reset while src active — catches the P0 bug class)
- A8: port connectivity (no X/Z on outputs)
- B7: cdc_single_bit port connectivity
- C6: cdc_handshake reset recovery + port connectivity
Full regression: 13/13 test suites pass (257 total assertions).
2026-03-17 19:38:09 +02:00
6fc5a10785
Fix range_bin_decimator overflow guard priority bug: group completion now takes precedence over overflow guard in ST_PROCESS, ensuring all OUTPUT_BINS outputs are emitted when sufficient input samples exist. Split formal property 5 into 5a (upper bound) and 5b (exact count when start_bin=0), added Cover 4 for overflow guard path, reduced BMC depth to 50.
2026-03-17 15:41:06 +02:00
37c8925df0
Merge branch 'NawfalMotii79:main' into main
2026-03-17 13:59:12 +02:00
5fd632bc47
Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator
...
CDC fixes across 6 RTL files based on post-implementation report_cdc analysis:
- P0: sync stm32_mixers_enable and new_chirp_pulse to clk_120m via toggle CDC
in radar_transmitter, add ft601 reset synchronizer and USB holding
registers with proper edge detection in usb_data_interface
- P1: add ASYNC_REG to edge_detector, convert new_chirp_frame to toggle CDC,
fix USB valid edge detect to use fully-synced signal
- P2: register Gray encoding in cdc_adc_to_processing source domain, sync
ft601_txe and stm32_mixers_enable for status_reg in radar_system_top
- Safety: add in_bin_count overflow guard in range_bin_decimator to prevent
downstream BRAM corruption
All 13 regression test suites pass (159 individual tests).
2026-03-17 13:48:47 +02:00
fb59e98737
Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs
...
Formal verification (SymbiYosys + smtbmc/z3):
- cdc_single_bit: BMC PASS depth 80, cover PASS 3/3
- cdc_handshake: BMC PASS depth 100, cover PASS 4/4
- cdc_adc_to_processing: BMC PASS depth 80, cover PASS
- radar_mode_controller: BMC PASS depth 200, cover PASS 8/8
- range_bin_decimator: cover PASS 7/7, BMC running (step 61+)
- doppler_processor: cover running (step 133/150), BMC running (step 35+)
DUT bug fixes found by formal:
- doppler_processor: write_chirp_index overflow past CHIRPS_PER_FRAME-1
in S_ACCUMULATE frame-complete branch (reset to 0)
- doppler_processor: read_doppler_index unclamped prefetch in S_LOAD_FFT
causing OOB BRAM reads (clamped to DOPPLER_FFT_SIZE-1)
CDC fix (prior session, included):
- cdc_modules: async reset changed to sync reset on all CDC sync chains
to prevent metastability on reset deassertion
RTL changes for formal observability:
- Added ifdef FORMAL output ports to cdc_handshake (6), cdc_adc (2),
radar_mode_controller (2), range_bin_decimator (5), doppler_processor (11)
2026-03-17 12:47:22 +02:00
0b52f49135
Added all boards stack
2026-03-17 02:26:23 +00:00
Jason
NawfalMotii79