d5d28e9f1c
Build 25 engineering report: MTI canceller + DC notch timing PASS
...
Build 25 results (MTI + DC notch integration):
- WNS +0.132 ns, WHS +0.058 ns (all domains PASS)
- 9,252 LUTs, 12,488 FFs, 17 BRAM, 142 DSP, 0.753 W
- MTI cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSP
- Bitstream: radar_system_top_build25.bit (production-safe)
- 23/23 FPGA regression, 29/29 MTI checks, 3/3 real-data co-sim
Updated reports.html (15-point Build 25 report), implementation-log.html
(timeline entries for production fixes, CFAR, MTI), and release-notes.html
(new tagged releases, gap status update).
2026-03-20 16:59:30 +02:00
19284ac277
Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21
...
Build 21 Vivado results extracted and documented:
- WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met)
- 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%)
- Total power: 0.732 W
- Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected
- TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug)
- Updated release-notes.html, implementation-log.html, reports.html
2026-03-20 02:21:33 +02:00
d2f20f5c15
Update docs for Build 20 (v0.1.3-build20) stable release + Gaps 3-7 status
...
- release-notes.html: Add commits for Gaps 3-5-7-4, tagged releases table,
architectural gap status table, updated GitHub links
- implementation-log.html: Add Build 20/19/18 timeline entries, Gap 3-4-5
milestones, updated quality/build history sections
- reports.html: Update FPGA status to Build 20 baseline, MCU regression
to 20/20, report currency notice with current gap status
2026-03-19 23:22:38 +02:00
Jason