FlintyLemming/PLFM_RADAR
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5 Commits

Author SHA1 Message Date
NawfalMotii79 d3476139e3 Merge pull request #89 from NawfalMotii79/feat/ft2232h-default-ft601-option 
feat: make FT2232H default USB interface, add FT601 premium option, deprecate GUI V6
 2026-04-17 22:21:58 +01:00
Jason a03dd1329a fix(tests): update cross-layer tests for frame_start bit and stream-gated mux 
- TB byte 9 check: expect 0x81 (frame_start=1 after reset + cfar=1)
- contract_parser: handle ternary expressions in data_pkt_byte mux
  (stream_doppler_en ? doppler_real_cap : 8'd0 pattern)
- contract_parser: handle intermediate variable pattern for detection
  field (det_byte = raw[9]; detection = det_byte & 0x01)
 2026-04-16 16:48:43 +05:45
JunghwanNA 029df375f5 fix(test): break on unknown signal in count_concat_bits 
When an unknown signal is encountered, total is set to -1 but the
loop continues. Subsequent known signals add their widths to -1,
producing incorrect totals (e.g. -1 + 16 = 15 instead of -1).
This can mask genuine truncation bugs in status word packing.
 2026-04-16 12:27:10 +09:00
Jason ffba27a10a feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix 
FPGA:
- rx_gain_control.v rewritten: per-frame peak/saturation tracking,
  auto-shift AGC with attack/decay/holdoff, signed gain -7 to +7
- New registers 0x28-0x2C (agc_enable/target/attack/decay/holdoff)
- status_words[4] carries AGC metrics (gain, peak, sat_count, enable)
- DIG_5 GPIO outputs saturation flag for STM32 outer loop
- Both USB interfaces (FT601 + FT2232H) updated with AGC status ports

Timing fix (WNS +0.001ns -> +0.045ns, 45x improvement):
- CIC max_fanout 4->16 on valid pipeline registers
- +200ps setup uncertainty on 400MHz domain
- ExtraNetDelay_high placement + AggressiveExplore routing

GUI:
- AGC opcodes + status parsing in radar_protocol.py
- AGC control groups in both tkinter and V7 PyQt dashboards
- 11 new AGC tests (103/103 GUI tests pass)

Cross-layer:
- AGC opcodes/defaults/status assertions added (29/29 pass)
- contract_parser.py: fixed comment stripping in concat parser

All tests green: 25 FPGA + 103 GUI + 29 cross-layer = 157 pass
 2026-04-13 19:24:11 +05:45
Jason 0537b40dcc feat: add cross-layer contract tests (Python/Verilog/C) with CI job 
Three-tier test orchestrator validates opcode maps, bit widths, packet
layouts, and round-trip correctness across FPGA RTL, Python GUI, and
STM32 firmware. Catches 3 real bugs:

- status_words[0] 37-bit truncation in both USB interfaces
- Python radar_mode readback at wrong bit position (bit 21 vs 24)
- RadarSettings.cpp buffer overread (min check 74 vs required 82)

29 tests: 24 pass, 5 xfail (documenting confirmed bugs).
4th CI job added: cross-layer-tests (Python + iverilog + cc).
 2026-04-12 16:04:59 +05:45