2 Commits

Author	SHA1	Message	Date
Jason	94ffdb8f77	Add Phase 0 Vivado-style lint to regression runner, update golden data ... Adds two-layer lint pass (iverilog -Wall + custom static checks) that catches part-select OOB errors and case-without-default warnings before pushing to remote Vivado. Catches the exact Synth 8-524 class error that broke Build 18 initial attempt. Lint errors abort regression; warnings are advisory. Regenerated golden data for BRAM-migrated matched filter.	2026-03-19 21:19:07 +02:00
Jason	463ebef554	CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner ... - cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and data_valid_comb_pipe pipeline stages between integrator sampling and comb computation to break the critical path (matches remote 40cda0f) - radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard with pass-through assigns for iverilog compatibility - radar_system_tb.v: Convert generate_radar_echo function to task and move sin_lut declaration before task (iverilog declaration-order fix), add modular index clamping to prevent LUT out-of-bounds - run_regression.sh: Automated regression runner for all 18 FPGA testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail - .gitignore: Exclude *.vvp, *.vcd simulation artifacts	2026-03-19 11:31:46 +02:00