f393e96d69
feat(fpga): make FT2232H default USB interface, rewrite FT601 write FSM, add clock-loss watchdog
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- Set USB_MODE default to 1 (FT2232H) in radar_system_top.v; 200T build
overrides to USB_MODE=0 via build_200t.tcl generic property
- Rewrite FT601 write FSM: 4-state architecture with 3-word packed data,
pending-flag gating, and frame sync counter
- Add FT2232H read FSM rd_cmd_complete flag, stream field zeroing, and
range_data_ready 1-cycle pipeline delay in both USB modules
- Implement clock-loss watchdog: ft_heartbeat toggle + 16-bit timeout
counter drives ft_clk_lost, feeding ft_effective_reset_n via 2-stage
ASYNC_REG synchronizer chain
- Fix sample_counter reset literal width (11'd0 -> 12'd0)
- Add FT2232H I/O timing constraints to 50T XDC; fix dac_clk comments
- Document vestigial ft601_txe_n/rxf_n ports (needed for 200T XDC)
- Tie off AGC ports on TE0713 dev wrapper
- Rewrite tb_usb_data_interface.v for new 4-state FSM (89 checks)
- Add USB_MODE=1 regression runs; remove dead CHECK 5/6 loop
- Update diag_log.h USB interface comment
2026-04-16 16:18:52 +05:45
e4db996db9
fix: remove server credentials from constraints README
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Accidentally included SSH key path, hostname, port, and internal server
paths in the build quick-reference section. Replaced with generic
instructions.
2026-04-07 21:37:30 +03:00
75854a39ca
docs: update constraints README with USB_MODE architecture and build guide
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Add USB Interface Architecture section documenting the USB_MODE parameter,
generate block mechanism, per-target wrapper pattern, FT2232H pin map, and
build quick-reference. Update top modules table (50T now uses
radar_system_top_50t), bank voltage tables, and signal differences to
reflect the FT2232H/FT601 dual-interface design.
2026-04-07 21:34:38 +03:00
967ce179eb
Add TE0713/TE0701 alternate dev target for in-stock SoM path
2026-03-18 15:02:09 +02:00
0ae7b40ff0
Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
2026-03-18 03:57:26 +02:00
49eb6169b6
Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB
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- Expand ft601_be from [1:0] to [3:0] across RTL, top-level, testbenches,
and XDC (uncomment be[2:3] pin assignments B21/A21)
- Fix NCO XSim testbench: correct reset check (0x7FFF not 0), add pipeline
warmup and sample skip for DSP48E1 quadrature test
- All local regression tests pass (39/39 USB, 10/10 integration, all co-sim)
2026-03-16 23:17:38 +02:00
1acedf494c
Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I
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Production FPGA: Artix-7 XC7A200T-2FBG484I (33,650 slices, 740 DSP48E1,
365 BRAM, -2 speed grade). Pin-mapped across 6 banks with proper VCCO
assignment (3.3V/2.5V/1.8V).
RTL timing primitives added for clean timing closure:
- ad9484_interface_400m.v: BUFIO for IDDR capture at 400MHz DDR,
BUFG for fabric logic, reset synchronizer (P1-7)
- dac_interface_single.v: ODDR for dac_clk forwarding + dac_data[7:0]
output registration, eliminates clock-forwarding insertion delay
- usb_data_interface.v: ODDR for ft601_clk_out forwarding, FSM runs
on ft601_clk_in domain with CDC synchronizers
Constraints:
- New production XDC (xc7a200t_fbg484.xdc): 182 pins, generated clocks
for ODDR outputs, BUFIO/DDR input delays, fixed false_path strategy
(from reset source, not to CLR pins), IOB packing on cells not ports
- Preserved upstream XDC as xc7a50t_ftg256.xdc for reference
- Updated cntrt.xdc with DRC fixes (I/O standards, missing constraints)
2026-03-16 22:24:22 +02:00
Jason