6 Commits

Author	SHA1	Message	Date
Jason	70067c6121	fix(fpga): F-0.1 wire AD9484 OR overrange pin into diagnostics ... The AD9484 OR (overrange) LVDS pair is routed on the 50T main board to xc7a50t-ftg256 bank-14 pins M6/N6 but was previously left unconnected at the top level. Plumb it through the full stack so saturation at the raw ADC boundary shows up in the existing overflow aggregation: - ad9484_interface_400m: add adc_or_p/n inputs, IBUFDS + IDDR capture of both phases in the BUFIO domain, re-register into the clk_400m BUFG domain, OR rise|fall into adc_overrange_400m output. - radar_receiver_final: stickify adc_overrange_400m in clk_400m, CDC to clk_100m via a 2FF ASYNC_REG chain (same reasoning as F-1.2's cdc_cic_fir_overrun — single-bit, latched low→high, GPIO-class diagnostic), OR into the existing ddc_overflow_any aggregation. - radar_system_top: expose adc_or_p/n top-level ports and pass through. - xc7a50t_ftg256.xdc: anchor M6/N6 as LVDS_25 DIFF_TERM, with the same DCO-relative input-delay constraints as adc_d_p[*]. - xc7a200t_fbg484.xdc: IOSTANDARD/DIFF_TERM set; PACKAGE_PIN left as a documented TODO — the 200T dev-board schematic has not been checked and the 200T build will need the anchor filled in before place/route.	2026-04-20 15:48:34 +05:45
Jason	d50e51ada6	fix(rtl,constraints): change IBUFDS to IOSTANDARD DEFAULT for multi-target bank voltage compatibility ... The IBUFDS primitives in ad9484_interface_400m.v hardcoded LVDS_25 and DIFF_TERM TRUE, which overrode XDC constraints. On the XC7A50T (Bank 14 VCCO=3.3V), this caused a BIVC-1 DRC error: LVDS_25 requires VCCO=2.5V, conflicting with adc_pwdn (LVCMOS33, VCCO=3.3V) in the same bank. Changes: - ad9484_interface_400m.v: IBUFDS parameters changed from LVDS_25/DIFF_TERM TRUE to DEFAULT/DIFF_TERM FALSE, delegating control to XDC per target - xc7a50t_ftg256.xdc: Re-enable DIFF_TERM TRUE (safe now that RTL does not hardcode LVDS_25), update DRC Fix History with correct root cause	2026-04-07 05:17:11 +03:00
Jason	c6103b37de	Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix ... MMCM (Gap 7): - Add adc_clk_mmcm.v: MMCME2_ADV wrapper (VCO=800MHz, CLKOUT0=400MHz) - Modify ad9484_interface_400m.v: replace BUFG with MMCM path, gate reset on mmcm_locked - Add adc_clk_mmcm.xdc: CDC false paths for clk_mmcm_out0 <-> clk_100m XDC Fix (Build 19 WNS=-0.011 root cause): - Remove conflicting create_generated_clock -name clk_400m_mmcm - Replace all clk_400m_mmcm references with Vivado auto-generated clk_mmcm_out0 - CDC false paths now correctly apply to actual timing paths CIC CREG Pipeline (Build 18 critical path fix): - Explicit DSP48E1 for comb[0] with CREG=1/AREG=1/BREG=1/PREG=1 - Absorbs integrator_sampled_comb fabric FDRE into DSP48 C-port register - Eliminates 0.643ns fabric->DSP routing delay (Build 18 tightest path) - +1 cycle comb latency via data_valid_comb_0_out pipeline - Move shared register declarations above ifndef SIMULATION (iverilog fix) - Update golden data for +1 cycle CIC pipeline shift Build scripts: build19_mmcm.tcl, build20_mmcm_creg.tcl Regression: 18/18 FPGA pass, 20/20 MCU pass Build 20 launched on remote Vivado (pending results)	2026-03-19 22:59:46 +02:00
Jason	1acedf494c	Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I ... Production FPGA: Artix-7 XC7A200T-2FBG484I (33,650 slices, 740 DSP48E1, 365 BRAM, -2 speed grade). Pin-mapped across 6 banks with proper VCCO assignment (3.3V/2.5V/1.8V). RTL timing primitives added for clean timing closure: - ad9484_interface_400m.v: BUFIO for IDDR capture at 400MHz DDR, BUFG for fabric logic, reset synchronizer (P1-7) - dac_interface_single.v: ODDR for dac_clk forwarding + dac_data[7:0] output registration, eliminates clock-forwarding insertion delay - usb_data_interface.v: ODDR for ft601_clk_out forwarding, FSM runs on ft601_clk_in domain with CDC synchronizers Constraints: - New production XDC (xc7a200t_fbg484.xdc): 182 pins, generated clocks for ODDR outputs, BUFIO/DDR input delays, fixed false_path strategy (from reset source, not to CLR pins), IOB packing on cells not ports - Preserved upstream XDC as xc7a50t_ftg256.xdc for reference - Updated cntrt.xdc with DRC fixes (I/O standards, missing constraints)	2026-03-16 22:24:22 +02:00
Jason	eefaf94e9e	Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis ... Resolves all synthesis errors across attempts 3-11, achieving clean Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs). radar_receiver_final.v: - reg clk_400m -> wire; output reg -> output wire (x4) - Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m - Remove duplicate IBUFDS lvds_to_cmos_400m instantiation - Remove non-existent ref_i/ref_q port connections on matched filter - Connect adc_dco_bufg as 400MHz clock source ad9484_interface_400m.v: - Add adc_dco_bufg output port with BUFG instance - Route all internal logic through buffered DCO clock cic_decimator_4x_enhanced.v: - Move reset_monitors handling inside else branch (fixes Vivado ambiguous clock error in both integrator and comb always blocks) - Add separate comb_overflow_latched/comb_saturation_detected regs to eliminate multi-driven nets between integrator and comb blocks - Remove standalone always @(posedge reset_monitors) block - Add output_counter to async reset branch matched_filter_processing_chain.v: - Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION - Add synthesis stub tying outputs to safe defaults chirp_memory_loader_param.v: - Replace hardcoded Windows paths with relative filenames for all 10 $readmem default parameters latency_buffer_2159.v: - Split single always block into separate BRAM write (synchronous only) and control logic (with async reset) blocks - Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset xfft_32.v (NEW): - Synthesis stub for Xilinx 32-point FFT IP core - AXI-Stream interface with pass-through and 1-cycle latency - Placeholder until real xfft IP is generated	2026-03-15 17:37:59 +02:00
NawfalMotii79	5fbe97fa5f	Add files via upload	2026-03-09 00:17:39 +00:00