063fa081fe
fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review
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FPGA timing (400MHz domain WNS: +0.339ns, was +0.002ns):
- DONT_TOUCH on BUFG to prevent AggressiveExplore cascade replication
- NCO→mixer pipeline registers break critical 1.5ns route
- Clock uncertainty reduced 200ps→100ps (adequate guardband)
- Updated golden/cosim references for +1 cycle pipeline latency
STM32 bug fixes:
- Guard uint32_t underflow in processStartFlag (length<4)
- Replace unbounded strcat in getSystemStatusForGUI with snprintf
- Early-return error masking in checkSystemHealth
- Add HAL_Delay in emergency blink loop
GUI bug fixes:
- Remove 0x03 from _HARDWARE_ONLY_OPCODES (was in both sets)
- Wire real error count in V7 diagnostics panel
- Fix _stop_demo showing 'Live' label during replay mode
FPGA comment fixes + CI: add test_v7.py to pytest command
Vivado build 50t passed: 0 failing endpoints, WHS=+0.056ns
2026-04-14 00:08:26 +05:45
b4d1869582
fix: 9 bugs from code review — RTL sign-ext & snapshot, thread safety, protocol fixes
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- rx_gain_control.v: sign-extension fix ({agc_gain[3],agc_gain} not {1'b0,agc_gain})
+ inclusive frame_boundary snapshot via combinational helpers (Bug #7 )
- v7/dashboard.py: Qt thread-safe logging via pyqtSignal bridge (Bug #1 )
+ table headers corrected to 'Range (m)' / 'Velocity (m/s)' (Bug #2 )
- main.cpp: guard outerAgc.applyGain() with if(outerAgc.enabled) (Bug #3 )
- radar_protocol.py: replay L1 threshold detection when CFAR disabled (Bug #4 )
+ IndexError guard in replay open (Bug #5 ) + AGC opcodes in _HARDWARE_ONLY_OPCODES
- radar_dashboard.py: AGC monitor attribute name fixes (3 labels)
- tb_rx_gain_control.v: Tests 17-19 (sign-ext, simultaneous valid+boundary, enable toggle)
- tb_cross_layer_ft2232h.v: AGC opcode vectors 0x28-0x2C in Exercise A (Bug #6 )
Vivado 50T build verified: WNS=+0.002ns, WHS=+0.028ns — all timing constraints met.
All tests pass: MCU 21/21, GUI 120/120, cross-layer 29/29, FPGA 25/25 (68 checks).
2026-04-13 23:35:10 +05:45
3ef6416e3f
feat: AGC phase 7 — AGC Monitor visualization tab with throttled redraws
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Add AGC Monitor tab to both tkinter and PyQt6 dashboards with:
- Real-time strip charts: gain history, peak magnitude, saturation count
- Color-coded indicator labels (green/yellow/red thresholds)
- Ring buffer architecture (deque maxlen=256, ~60s at 10 Hz)
- Fill-between saturation area with auto-scaling Y axis
- Throttled matplotlib redraws (500ms interval via time.monotonic)
to prevent GUI hang from 20 Hz mock-mode status packets
Tests: 82 dashboard + 38 v7 = 120 total, all passing. Ruff: clean.
2026-04-13 20:42:01 +05:45
ffba27a10a
feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix
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FPGA:
- rx_gain_control.v rewritten: per-frame peak/saturation tracking,
auto-shift AGC with attack/decay/holdoff, signed gain -7 to +7
- New registers 0x28-0x2C (agc_enable/target/attack/decay/holdoff)
- status_words[4] carries AGC metrics (gain, peak, sat_count, enable)
- DIG_5 GPIO outputs saturation flag for STM32 outer loop
- Both USB interfaces (FT601 + FT2232H) updated with AGC status ports
Timing fix (WNS +0.001ns -> +0.045ns, 45x improvement):
- CIC max_fanout 4->16 on valid pipeline registers
- +200ps setup uncertainty on 400MHz domain
- ExtraNetDelay_high placement + AggressiveExplore routing
GUI:
- AGC opcodes + status parsing in radar_protocol.py
- AGC control groups in both tkinter and V7 PyQt dashboards
- 11 new AGC tests (103/103 GUI tests pass)
Cross-layer:
- AGC opcodes/defaults/status assertions added (29/29 pass)
- contract_parser.py: fixed comment stripping in concat parser
All tests green: 25 FPGA + 103 GUI + 29 cross-layer = 157 pass
2026-04-13 19:24:11 +05:45
2106e24952
fix: enforce strict ruff lint (17 rule sets) across entire repo
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- Expand ruff config from E/F to 17 rule sets (B, RUF, SIM, PIE, T20,
ARG, ERA, A, BLE, RET, ISC, TCH, UP, C4, PERF)
- Fix 907 lint errors across all Python files (GUI, FPGA cosim,
schematics scripts, simulations, utilities, tools)
- Replace all blind except-Exception with specific exception types
- Remove commented-out dead code (ERA001) from cosim/simulation files
- Modernize typing: deprecated typing.List/Dict/Tuple to builtins
- Fix unused args/loop vars, ambiguous unicode, perf anti-patterns
- Delete legacy GUI files V1-V4
- Add V7 test suite, requirements files
- All CI jobs pass: ruff (0 errors), py_compile, pytest (92/92),
MCU tests (20/20), FPGA regression (25/25)
2026-04-12 14:21:03 +05:45
11aa590cf2
fix: full-repo ruff lint cleanup and CI migration to uv
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Resolve all 374 ruff errors across 36 Python files (E501, E702, E722,
E741, F821, F841, invalid-syntax) bringing `ruff check .` to zero
errors repo-wide with line-length=100.
Rewrite CI workflow to use uv for dependency management, whole-repo
`ruff check .`, py_compile syntax gate, and merged python-tests job.
Add pyproject.toml with ruff config and uv dependency groups.
CI structure proposed by hcm444.
2026-04-09 02:05:34 +03:00
57de32b172
fix: resolve all ruff lint errors across V6+ GUIs, v7 module, and FPGA cosim scripts
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Fixes 25 remaining manual lint errors after auto-fix pass (94 auto-fixed earlier):
- GUI_V6.py: noqa on availability imports, bare except, unused vars, F811 redefs
- GUI_V6_Demo.py: unused app variable
- v7/models.py: noqa F401 on 8 try/except availability-check imports
- FPGA cosim: unused header/status/span vars, ambiguous 'l' renamed to 'line',
E701 while-on-one-line split, F841 padding vars annotated
Also adds v7/ module, GUI_PyQt_Map.py, and GUI_V7_PyQt.py to version control.
Expands CI lint job to cover all 21 maintained Python files (was 4).
All 58 Python tests pass. Zero ruff errors on all target files.
2026-04-08 19:11:40 +03:00
Jason