3 Commits

Author	SHA1	Message	Date
Jason	49eb6169b6	Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB ... - Expand ft601_be from [1:0] to [3:0] across RTL, top-level, testbenches, and XDC (uncomment be[2:3] pin assignments B21/A21) - Fix NCO XSim testbench: correct reset check (0x7FFF not 0), add pipeline warmup and sample skip for DSP48E1 quadrature test - All local regression tests pass (39/39 USB, 10/10 integration, all co-sim)	2026-03-16 23:17:38 +02:00
Jason	f154edbd20	Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001 ... - Regenerate all 10 chirp .mem files with correct AERIS-10 parameters (gen_chirp_mem.py: phase = pi*chirp_rate*t^2, 4 segments x 1024) - Add gen_chirp_mem.py script for reproducible .mem generation - Add tb_usb_data_interface.v testbench (39/39 PASS) - Convert radar_system_tb.v from SystemVerilog to Verilog-2001: replace $sin() with LUT, inline integer decl, SVA with procedural checks - All testbenches pass: integration 10/10, MF 3/3, multi-seg 32/32, DDC 4/4, Doppler 14/14, USB 39/39, .mem validation 56/56 - Vivado timing closure confirmed: WNS=+0.021ns on xc7a100t-csg324-1	2026-03-16 19:53:40 +02:00
NawfalMotii79	220f2e0d0b	Create radar_system_tb.v	2026-03-10 01:35:26 +00:00