 Jason
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558f49cd4a
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Add 8 Verilog testbenches with full coverage (144/144 pass)
Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).
Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.
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2026-03-15 06:14:11 +02:00 |
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Jason
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76183e2e95
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Fix 6 RTL bugs in FPGA signal processing chain
- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port
All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).
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2026-03-15 06:14:04 +02:00 |
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NawfalMotii79