e76925391c
Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)
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RTL fix: matched_filter_multi_segment.v ST_WAIT_FFT now waits for
processing chain to complete ALL 1024 outputs and return to IDLE
before advancing to next segment. Previously, it transitioned on the
first fft_pc_valid edge, causing the chain to still be outputting
while multi-seg started collecting data for the next segment. This
broke the handshake and caused permanent deadlock after segment 0.
Also fixes forward reference of sample_addr_from_chain in
radar_receiver_final.v (declaration moved before first use).
New files:
- tb/tb_radar_receiver_final.v: P0 integration test for full RX
pipeline (ADC->DDC->MF->range_bin_decimator->doppler), 10 checks
- tb/ad9484_interface_400m_stub.v: behavioral ADC stub for iverilog
All existing tests still pass: multi-seg 32/32, MF co-sim 3/3,
Doppler co-sim 14/14.
2026-03-16 18:51:08 +02:00
a5a5e96a57
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
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Bug: rounding logic 'adc_i <= ddc_i[17:2] + ddc_i[1]' overflows when
ddc_i[17:2]=0x7FFF and ddc_i[1]=1, causing 0x7FFF+1=0x8000 (sign flip
from max positive to most negative value).
Fix: add explicit saturation — clamp to 0x7FFF when truncated value is
max positive and round bit is set. Negative values cannot overflow since
rounding only moves toward zero.
New testbench: tb_ddc_input_interface.v with 26 tests covering rounding,
truncation, overflow saturation at positive boundary, negative full scale,
valid synchronization, and sync error detection.
2026-03-16 18:14:06 +02:00
17731dd482
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
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RTL bug fixes:
- doppler_processor.v: Add S_PRE_READ state to prime BRAM pipeline, restructure
S_LOAD_FFT with sub-counter staging, fix BRAM address off-by-one
(read_doppler_index <= fft_sample_counter + 2, was +1). All 3 Doppler
co-sim scenarios now achieve BIT-PERFECT match (correlation=1.0, energy=1.0).
- matched_filter_multi_segment.v: Move buffer_write_ptr >= SEGMENT_ADVANCE check
outside if(ddc_valid) block to prevent FSM deadlock. 32/32 tests PASS.
New co-simulation infrastructure:
- Doppler co-sim: tb_doppler_cosim.v (14/14 structural checks),
gen_doppler_golden.py (3 scenarios: stationary/moving/two_targets),
compare_doppler.py (bit-perfect thresholds)
- Multi-segment co-sim: tb_multiseg_cosim.v (32/32), gen_multiseg_golden.py
with short and long test vector suites
2026-03-16 18:09:26 +02:00
e506a80db5
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
baa24fd01e
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
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Bit-accurate Python model (fpga_model.py) mirrors full DDC RTL chain:
NCO -> mixer -> CIC -> FIR with exact fixed-point arithmetic matching
RTL DSP48E1 pipeline behavior including CREG=1 delay on CIC int_0.
Synthetic radar scene generator (radar_scene.py) produces ADC test
vectors for 5 scenarios: DC, single target (500m), multi-target (5),
noise-only, and 1 MHz sine wave.
DDC co-sim testbench (tb_ddc_cosim.v) feeds hex vectors through RTL
DDC and exports baseband I/Q to CSV. All 5 scenarios compile and run
with Icarus Verilog (iverilog -g2001 -DSIMULATION).
Comparison framework (compare.py) validates Python vs RTL using
statistical metrics (RMS ratio, DC offset, peak ratio) rather than
exact sample match due to RTL LFSR phase dithering. Results: 5/5 PASS.
2026-03-16 16:01:40 +02:00
00fbab6c9d
Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)
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Complete FPGA timing closure across all clock domains after 9 iterative
Vivado builds. WNS improved from -48.325ns to +0.018ns (107,886 endpoints).
RTL fixes for 400 MHz timing:
- NCO: 6-stage pipeline with DSP48E1 phase accumulator, registered LUT
index (Fix D splits address decode from ROM read), distributed RAM
- CIC: explicit DSP48E1 PCOUT->PCIN cascade for 5 integrator stages,
CREG=1 on integrator_0 to eliminate fabric->DSP setup violation
- DDC: 400 MHz reset synchronizer (async-assert/sync-deassert),
active-high reset register for DSP48E1 RST ports, posedge output stage
- FIR: 5-stage binary adder tree pipeline (7-cycle latency)
- FFT: 5-cycle butterfly pipeline with registered twiddle index,
XPM_MEMORY_TDPRAM for data storage
- XDC: CDC false paths, async reset false paths, CIC comb multicycle paths
Final Build 9 timing (all MET):
adc_dco_p (400 MHz): WNS = +0.278ns
clk_100m (100 MHz): WNS = +0.018ns
clk_120m_dac (120 MHz): WNS = +0.992ns
ft601_clk_in (100 MHz): WNS = +5.229ns
Cross-domain (adc_dco_p->clk_100m): WNS = +7.105ns
2026-03-16 15:02:35 +02:00
692b6a3bfa
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
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Implement iterative single-butterfly FFT engine (fft_engine.v) supporting
1024-pt and 32-pt transforms with quarter-wave twiddle ROM, XPM_MEMORY_TDPRAM
for guaranteed BRAM mapping in Vivado, and behavioral model for simulation.
Add xfft_32.v AXI-Stream wrapper for doppler_processor integration and
dual-branch matched_filter_processing_chain.v (behavioral + synthesis paths).
Fix placement failure caused by 68K+ registers from dissolved memory arrays:
- doppler_processor.v: extract mem writes to sync-only always block for BRAM
- xfft_32.v: extract buffer writes to sync-only always block for LUTRAM
Post-implementation: 37K regs (29%), 23K LUTs (37%), 10 BRAM (7%), fully routed.
All testbenches pass: fft_engine 12/12, xfft_32 10/10, mf_chain 27/27.
2026-03-16 10:25:07 +02:00
deb2e81ec4
Merge branch 'main' of https://github.com/JJassonn69/PLFM_RADAR
2026-03-16 01:02:17 +02:00
c983a3c705
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
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Phase 0+ timing optimization (attempts #13-22 + implementation):
NCO (nco_400m_enhanced.v):
- 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX
- DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain)
- Registered phase_inc_dithered to break cascaded 32-bit add path
DDC (ddc_400m.v):
- Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1)
- CEP=1, RSTP=!reset_n for proper pipeline control
- 3-stage dsp_valid_pipe for PREG=1 latency
- Behavioral sim model under ifdef SIMULATION for Icarus compatibility
CIC (cic_decimator_4x_enhanced.v):
- 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28
- Removed integrator/comb saturation (CIC uses wrapping arithmetic by design)
- Pipelined output saturation comparison
CDC/ASYNC_REG:
- ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v,
radar_system_top.v, usb_data_interface.v)
- Sync reset in generate blocks (cdc_modules.v)
Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints,
850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t.
All testbenches pass: 241/244 (3 known stub failures).
2026-03-16 01:02:07 +02:00
653098214c
Merge branch 'NawfalMotii79:main' into main
2026-03-16 00:51:55 +02:00
a9cd7bab2d
Add files via upload
2026-03-15 22:25:02 +00:00
e0ff3b1bc5
Add files via upload
2026-03-15 22:03:54 +00:00
70e8366dc4
Correct contributor name in license section
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Updated contributor acknowledgment in the license explanation.
2026-03-15 21:46:03 +00:00
415db19353
Update model name from AERIS-10X to AERIS-10E
2026-03-15 21:44:01 +00:00
1e51b739a7
Add missing long_chirp_seg3 memory files for complete chirp waveform
2026-03-15 18:06:35 +02:00
ffed7c1623
Fix CDC timing violations: add synchronizers for all inter-clock crossings
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Resolve all 4 inter-clock timing violations found in Vivado synthesis
attempt #11 (WNS was -2.552 ns). Changes:
- Add reset synchronizer for clk_120m_dac domain (2-FF chain)
- Add Gray-code CDC for chirp_counter (6-bit, 120MHz->100MHz)
- Add single-bit CDC for new_chirp_frame (3-stage, 120MHz->100MHz)
- Add 2-stage input synchronizers for valid signals in USB module
(clk_100m->ft601_clk_in) with data capture on rising edge
- Fix ft601_clk_out multi-driven net (removed duplicate assignment)
- Update XDC: set_max_delay -datapath_only for CDC, false_path for reset
Result: Vivado attempt #12 passes with 0 errors, 0 timing violations,
and 'All user specified timing constraints are met.' (WNS +0.983 ns)
2026-03-15 17:58:14 +02:00
eefaf94e9e
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
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Resolves all synthesis errors across attempts 3-11, achieving clean
Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs).
radar_receiver_final.v:
- reg clk_400m -> wire; output reg -> output wire (x4)
- Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m
- Remove duplicate IBUFDS lvds_to_cmos_400m instantiation
- Remove non-existent ref_i/ref_q port connections on matched filter
- Connect adc_dco_bufg as 400MHz clock source
ad9484_interface_400m.v:
- Add adc_dco_bufg output port with BUFG instance
- Route all internal logic through buffered DCO clock
cic_decimator_4x_enhanced.v:
- Move reset_monitors handling inside else branch (fixes Vivado
ambiguous clock error in both integrator and comb always blocks)
- Add separate comb_overflow_latched/comb_saturation_detected regs
to eliminate multi-driven nets between integrator and comb blocks
- Remove standalone always @(posedge reset_monitors) block
- Add output_counter to async reset branch
matched_filter_processing_chain.v:
- Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION
- Add synthesis stub tying outputs to safe defaults
chirp_memory_loader_param.v:
- Replace hardcoded Windows paths with relative filenames for all
10 $readmem default parameters
latency_buffer_2159.v:
- Split single always block into separate BRAM write (synchronous
only) and control logic (with async reset) blocks
- Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset
xfft_32.v (NEW):
- Synthesis stub for Xilinx 32-point FFT IP core
- AXI-Stream interface with pass-through and 1-cycle latency
- Placeholder until real xfft IP is generated
2026-03-15 17:37:59 +02:00
c871281f1e
Fix synthesis blockers in 9 RTL files for Vivado compatibility
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Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)
Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)
2026-03-15 14:53:35 +02:00
f5a3394f23
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
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Implement the 3 modules identified as missing during repo audit:
- matched_filter_processing_chain: behavioral FFT-based pulse compression
- range_bin_decimator: 1024→64 bin decimation with 3 modes + start_bin
- radar_mode_controller: 4-mode beam/chirp controller
Wire radar_mode_controller into radar_receiver_final.v to drive the
previously-undriven use_long_chirp and mc_new_* signals.
Implement start_bin functionality in range_bin_decimator (was dead code
in the original interface contract — now skips N input bins before
decimation for region-of-interest selection).
Add comprehensive testbenches with Tier 1 confidence improvements:
- Golden reference co-simulation (Python FFT → hex → bin comparison)
- Saturation boundary tests (0x7FFF / 0x8000 extremes)
- Reset mid-operation recovery tests
- Valid-gap / stall handling tests
- Mode switching and counter persistence tests
- Accumulator overflow stress tests
Test counts: matched_filter 40/40, range_bin_decimator 55/55,
radar_mode_controller 73/73 — all passing with iverilog -g2001.
2026-03-15 13:37:10 +02:00
81435f9ff9
Merge branch 'main' of https://github.com/NawfalMotii79/PLFM_RADAR
2026-03-15 06:22:27 +02:00
558f49cd4a
Add 8 Verilog testbenches with full coverage (144/144 pass)
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Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).
Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.
2026-03-15 06:14:11 +02:00
76183e2e95
Fix 6 RTL bugs in FPGA signal processing chain
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- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port
All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).
2026-03-15 06:14:04 +02:00
74d5a76abb
Merge pull request #7 from walidb212/fix/gy85-i2c-status
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fix(firmware): propagate gy85 i2c failures
2026-03-15 01:57:28 +00:00
eca26f413d
Merge pull request #6 from walidb212/refactor/adar-sequencing-constants
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refactor(firmware): name adar power sequencing constants
2026-03-15 01:56:59 +00:00
e212c806d4
Merge pull request #5 from walidb212/fix/gps-transport-status
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fix(firmware): return gps transport status
2026-03-15 01:56:16 +00:00
63c0aedc3b
Merge pull request #8 from walidb212/fix/gui-settings-validation
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fix(gui): validate radar settings before usb send
2026-03-15 00:52:05 +00:00
246d088169
Update README with licensing details
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Added hardware and software licensing information to the README, detailing the CERN Open Hardware License for hardware and the MIT License for software.
2026-03-15 00:39:23 +00:00
eed253cab0
Add CERN Open Hardware Licence Version 2 - Permissive
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This commit adds the CERN Open Hardware Licence Version 2 - Permissive to the project, providing legal guidelines for hardware design dissemination and collaboration.
2026-03-15 00:34:27 +00:00
a4b8a144ed
fix(firmware): return gps transport status
2026-03-13 19:41:45 +01:00
9bb6080a73
fix(firmware): propagate gy85 i2c failures
2026-03-13 19:38:42 +01:00
b1cb897275
refactor(firmware): name adar power sequencing constants
2026-03-13 19:32:10 +01:00
2d62d4320c
fix(gui): validate radar settings before usb send
2026-03-13 19:28:35 +01:00
7510e31c20
Update image path for AERIS-10 Radar System
2026-03-11 02:04:42 +00:00
19bcbba835
Add files via upload
2026-03-11 02:02:03 +00:00
4781ab1001
Include radar system image in README
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Add image of AERIS-10 Radar System to README
2026-03-11 02:01:34 +00:00
ea3319353b
Add files via upload
2026-03-10 23:39:49 +00:00
8896ed3814
Delete 1_Executive Summary directory
2026-03-10 23:39:12 +00:00
7b6f93955f
Create cntrt.xdc
2026-03-10 02:42:15 +00:00
a4a9c9ad00
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2026-03-10 02:17:36 +00:00
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2026-03-10 02:17:16 +00:00
11089dfacd
Update GUI_V6_Demo.py
2026-03-10 01:55:47 +00:00
90bab6bd64
Create GUI_V6_Demo.py
2026-03-10 01:43:19 +00:00
a7e55c752f
Create usb_packet_analyzer.v
2026-03-10 01:36:04 +00:00
220f2e0d0b
Create radar_system_tb.v
2026-03-10 01:35:26 +00:00
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2026-03-10 01:31:50 +00:00
0eb2d9726d
Update GUI_versions.txt
2026-03-10 01:27:05 +00:00
43ff85e331
Update and rename GUI_V6 to GUI_V6.py
2026-03-10 01:26:00 +00:00
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969e65272f
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2026-03-10 01:13:18 +00:00
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NawfalMotii79
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