4 Commits

Author	SHA1	Message	Date
Jason	1f315a62c8	fix(scripts,constraints): handle empty STATS properties in build summaries, fix 50T XDC DRC errors ... Build scripts (17-21): STATS.WNS/TNS/WHS/THS/TPWS from get_property can return empty strings in Vivado 2025.2 after write_bitstream auto-launch. Wrap in catch with N/A fallback. Guard all expr delta calculations and signoff comparisons with [string is double -strict] checks. XDC (xc7a50t_ftg256): Fix PLIO-9 by moving clk_120m_dac from C13 (N-type) to D13 (P-type MRCC) — clock inputs require P-type MRCC pin. Fix BIVC-1 by disabling DIFF_TERM on Bank 14 LVDS pairs to resolve VCCO conflict with single-ended adc_pwdn (LVCMOS33) on T5 — requires external termination.	2026-04-07 05:07:14 +03:00
Jason	6657e117d6	fix(scripts): fix TCL command substitution and impl status race in all 5 build scripts ... - Escape [extra] → \[extra\] to prevent TCL interpreting it as a command (Vivado resolved 'extra' to 'extract_files' causing ERROR [Common 17-163]) - Fix implementation status check: accept 'write_bitstream' status as success (Vivado auto-proceeds to write_bitstream, making status != '*Complete*') - Wrap bitstream launch_runs in catch{} to handle already-running case Fixes applied to: build17, build18, build19, build20, build21	2026-04-07 04:07:07 +03:00
Serhii	48b3847256	fix(scripts): make Vivado TCL scripts portable and update RTL file lists ... - Replace hardcoded /home/jason-stone/ paths with [info script]-relative path resolution in all 9 scripts (build17-21, insert_ila_probes, program_fpga, ila_capture, run_cdc_and_netlist) - Point constraint references at tracked XDC files instead of untracked synth_only.xdc - Remove six phantom RTL entries (chirp_lut_init.v, fft_1024_forward.v, fft_1024_inverse.v, level_shifter_interface.v, lvds_to_cmos_400m.v, usb_packet_analyzer.v) - Add six existing modules to file lists (rx_gain_control.v, mti_canceller.v, cfar_ca.v, fpga_self_test.v, xfft_16.v, adc_clk_mmcm.v) Closes #38	2026-04-06 22:53:42 +03:00
Jason	c6103b37de	Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix ... MMCM (Gap 7): - Add adc_clk_mmcm.v: MMCME2_ADV wrapper (VCO=800MHz, CLKOUT0=400MHz) - Modify ad9484_interface_400m.v: replace BUFG with MMCM path, gate reset on mmcm_locked - Add adc_clk_mmcm.xdc: CDC false paths for clk_mmcm_out0 <-> clk_100m XDC Fix (Build 19 WNS=-0.011 root cause): - Remove conflicting create_generated_clock -name clk_400m_mmcm - Replace all clk_400m_mmcm references with Vivado auto-generated clk_mmcm_out0 - CDC false paths now correctly apply to actual timing paths CIC CREG Pipeline (Build 18 critical path fix): - Explicit DSP48E1 for comb[0] with CREG=1/AREG=1/BREG=1/PREG=1 - Absorbs integrator_sampled_comb fabric FDRE into DSP48 C-port register - Eliminates 0.643ns fabric->DSP routing delay (Build 18 tightest path) - +1 cycle comb latency via data_valid_comb_0_out pipeline - Move shared register declarations above ifndef SIMULATION (iverilog fix) - Update golden data for +1 cycle CIC pipeline shift Build scripts: build19_mmcm.tcl, build20_mmcm_creg.tcl Regression: 18/18 FPGA pass, 20/20 MCU pass Build 20 launched on remote Vivado (pending results)	2026-03-19 22:59:46 +02:00