 Serhii
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48b3847256
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fix(scripts): make Vivado TCL scripts portable and update RTL file lists
- Replace hardcoded /home/jason-stone/ paths with [info script]-relative
path resolution in all 9 scripts (build17-21, insert_ila_probes,
program_fpga, ila_capture, run_cdc_and_netlist)
- Point constraint references at tracked XDC files instead of
untracked synth_only.xdc
- Remove six phantom RTL entries (chirp_lut_init.v, fft_1024_forward.v,
fft_1024_inverse.v, level_shifter_interface.v, lvds_to_cmos_400m.v,
usb_packet_analyzer.v)
- Add six existing modules to file lists (rx_gain_control.v,
mti_canceller.v, cfar_ca.v, fpga_self_test.v, xfft_16.v,
adc_clk_mmcm.v)
Closes #38
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2026-04-06 22:53:42 +03:00 |
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 Jason
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f6877aab64
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Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
- Rename latency_buffer_2159 -> latency_buffer (module + file + all refs)
- Add CDC waivers for 5 verified false-positive criticals to XDC
- Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains)
- Add FPGA programming script (7-step flow with DONE pin verification)
- Add ILA capture script (4 scenarios + health check, CSV export)
- Add debug_ila.xdc with MARK_DEBUG fallback attributes
- Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match
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2026-03-18 01:28:42 +02:00 |
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