 Jason
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f154edbd20
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Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
- Regenerate all 10 chirp .mem files with correct AERIS-10 parameters
(gen_chirp_mem.py: phase = pi*chirp_rate*t^2, 4 segments x 1024)
- Add gen_chirp_mem.py script for reproducible .mem generation
- Add tb_usb_data_interface.v testbench (39/39 PASS)
- Convert radar_system_tb.v from SystemVerilog to Verilog-2001:
replace $sin() with LUT, inline integer decl, SVA with procedural checks
- All testbenches pass: integration 10/10, MF 3/3, multi-seg 32/32,
DDC 4/4, Doppler 14/14, USB 39/39, .mem validation 56/56
- Vivado timing closure confirmed: WNS=+0.021ns on xc7a100t-csg324-1
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2026-03-16 19:53:40 +02:00 |
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NawfalMotii79