FlintyLemming/PLFM_RADAR
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12 Commits

Author SHA1 Message Date
Jason 0773001708 E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA) 
RTL fixes discovered via new end-to-end testbench:
- plfm_chirp_controller: TX/RX mixer enables now mutually exclusive
  by FSM state (Fix #4), preventing simultaneous TX+RX activation
- usb_data_interface: stream control reset default 3'b001 (range-only),
  added doppler/cfar data_pending sticky flags, write FSM triggers on
  range_valid only — eliminates startup deadlock (Fix #5)
- radar_receiver_final: STM32 toggle signals wired through for mode-00
  pass-through, dynamic frame detection via host_chirps_per_elev
- radar_system_top: STM32 toggle signal wiring to receiver instance
- chirp_memory_loader_param: explicit readmemh range for short chirp

Test infrastructure:
- New tb_system_e2e.v: 46 checks across 12 groups (reset, TX, safety,
  RX, USB R/W, CDC, beam scanning, reset recovery, stream control,
  latency budgets, watchdog)
- tb_usb_data_interface: Tests 21/22/56 updated for data_pending
  architecture (preload flags, verify consumption instead of state)
- tb_chirp_controller: mixer tests T7.1/T7.2 updated for Fix #4
- run_regression.sh: PASS/FAIL regex fixed to match only [PASS]/[FAIL]
  markers, added E2E test entry
- Updated rx_final_doppler_out.csv golden data
 2026-03-20 01:45:00 +02:00
Jason 7cdfa486e5 Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU) 
Register map: 0x10-0x15 chirp timing overrides, 0xFF status readback,
0x03 CFAR threshold now wired to actual compare, 0x04 stream control
gates USB write FSM. Status readback sends 7-word packet (0xBB header,
5 status words, 0x55 footer) via toggle CDC.

radar_mode_controller: 6 cfg_* input ports replace hardcoded parameters.
usb_data_interface: stream_control CDC, status_request toggle CDC,
  SEND_STATUS state (3'd7), stream gating in IDLE/HEADER/RANGE/DOPPLER.
radar_system_top: 6 host registers + command decode for 0x10-0x15/0xFF.
radar_receiver_final: 6 host_* timing passthrough ports.

Testbench coverage: RMC 81 checks (+TG16 runtime reconfig), USB 77
checks (+TG15 stream gating, TG16 status readback, TG17 chirp opcodes).
Fixed iverilog 13.0 forward-ref for status_req_toggle_100m.
 2026-03-19 23:54:48 +02:00
Jason e5d1b3cfc3 Gap 4 USB Read Path: wire host-to-FPGA command path with toggle CDC, add read path tests 
- usb_data_interface.v: Add FT601 read FSM (RD_IDLE/OE_ASSERT/READING/
  DEASSERT/PROCESS) + cmd_data/valid/opcode/addr/value output ports
- radar_system_top.v: Connect cmd_* ports from usb_inst, add toggle CDC
  for cmd_valid (ft601_clk -> clk_100m), add command decode registers
  (mode/trigger/cfar_threshold/stream_control), wire host_mode and
  host_trigger to rx_inst
- radar_receiver_final.v: Add host_mode[1:0] and host_trigger input
  ports, replace hardcoded mode/trigger in radar_mode_controller instance
- tb_usb_data_interface.v: Connect cmd_* ports, add host data bus driver,
  add Test Groups 12 (single command), 13 (multiple commands), 14
  (read/write interleave). USB TB now has 55 checks.

Regression: 18/18 PASS
 2026-03-19 23:16:26 +02:00
Jason 3fa26c9e4c Wire matched filter range profile to USB, replacing Doppler placeholder 2026-03-19 12:33:40 +02:00
Jason f6877aab64 Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts 
- Rename latency_buffer_2159 -> latency_buffer (module + file + all refs)
- Add CDC waivers for 5 verified false-positive criticals to XDC
- Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains)
- Add FPGA programming script (7-step flow with DONE pin verification)
- Add ILA capture script (4 scenarios + health check, CSV export)
- Add debug_ila.xdc with MARK_DEBUG fallback attributes
- Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match
 2026-03-18 01:28:42 +02:00
Jason fd6094ee9e Fix P0/P1 RTL bugs found during pre-hardware audit 
P0-1: nco_400m_enhanced.v — DSP48E1 OPMODE corrected from PCIN to P
      feedback (was routing stale cascade data into accumulator)
P0-2: radar_receiver_final.v — removed same-clock CDC that corrupted
      ADC data path between ad9484_interface and DDC
P1-5: fir_lowpass.v — fixed zero replication count in coefficient
      symmetric extension ({0{1'b0}} is empty, now uses explicit 0)

Also updates .gitignore to exclude debug/scratch artifacts.

All 30+ testbenches pass (unit, co-sim, integration).
 2026-03-16 22:24:06 +02:00
Jason e76925391c Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS) 
RTL fix: matched_filter_multi_segment.v ST_WAIT_FFT now waits for
processing chain to complete ALL 1024 outputs and return to IDLE
before advancing to next segment. Previously, it transitioned on the
first fft_pc_valid edge, causing the chain to still be outputting
while multi-seg started collecting data for the next segment. This
broke the handshake and caused permanent deadlock after segment 0.

Also fixes forward reference of sample_addr_from_chain in
radar_receiver_final.v (declaration moved before first use).

New files:
- tb/tb_radar_receiver_final.v: P0 integration test for full RX
  pipeline (ADC->DDC->MF->range_bin_decimator->doppler), 10 checks
- tb/ad9484_interface_400m_stub.v: behavioral ADC stub for iverilog

All existing tests still pass: multi-seg 32/32, MF co-sim 3/3,
Doppler co-sim 14/14.
 2026-03-16 18:51:08 +02:00
Jason eefaf94e9e Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis 
Resolves all synthesis errors across attempts 3-11, achieving clean
Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs).

radar_receiver_final.v:
- reg clk_400m -> wire; output reg -> output wire (x4)
- Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m
- Remove duplicate IBUFDS lvds_to_cmos_400m instantiation
- Remove non-existent ref_i/ref_q port connections on matched filter
- Connect adc_dco_bufg as 400MHz clock source

ad9484_interface_400m.v:
- Add adc_dco_bufg output port with BUFG instance
- Route all internal logic through buffered DCO clock

cic_decimator_4x_enhanced.v:
- Move reset_monitors handling inside else branch (fixes Vivado
  ambiguous clock error in both integrator and comb always blocks)
- Add separate comb_overflow_latched/comb_saturation_detected regs
  to eliminate multi-driven nets between integrator and comb blocks
- Remove standalone always @(posedge reset_monitors) block
- Add output_counter to async reset branch

matched_filter_processing_chain.v:
- Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION
- Add synthesis stub tying outputs to safe defaults

chirp_memory_loader_param.v:
- Replace hardcoded Windows paths with relative filenames for all
  10 $readmem default parameters

latency_buffer_2159.v:
- Split single always block into separate BRAM write (synchronous
  only) and control logic (with async reset) blocks
- Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset

xfft_32.v (NEW):
- Synthesis stub for Xilinx 32-point FFT IP core
- AXI-Stream interface with pass-through and 1-cycle latency
- Placeholder until real xfft IP is generated
 2026-03-15 17:37:59 +02:00
Jason c871281f1e Fix synthesis blockers in 9 RTL files for Vivado compatibility 
Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)
 2026-03-15 14:53:35 +02:00
Jason f5a3394f23 Add 3 missing FPGA modules with enhanced testbenches (168/168 pass) 
Implement the 3 modules identified as missing during repo audit:
- matched_filter_processing_chain: behavioral FFT-based pulse compression
- range_bin_decimator: 1024→64 bin decimation with 3 modes + start_bin
- radar_mode_controller: 4-mode beam/chirp controller

Wire radar_mode_controller into radar_receiver_final.v to drive the
previously-undriven use_long_chirp and mc_new_* signals.

Implement start_bin functionality in range_bin_decimator (was dead code
in the original interface contract — now skips N input bins before
decimation for region-of-interest selection).

Add comprehensive testbenches with Tier 1 confidence improvements:
- Golden reference co-simulation (Python FFT → hex → bin comparison)
- Saturation boundary tests (0x7FFF / 0x8000 extremes)
- Reset mid-operation recovery tests
- Valid-gap / stall handling tests
- Mode switching and counter persistence tests
- Accumulator overflow stress tests

Test counts: matched_filter 40/40, range_bin_decimator 55/55,
radar_mode_controller 73/73 — all passing with iverilog -g2001.
 2026-03-15 13:37:10 +02:00
Jason 76183e2e95 Fix 6 RTL bugs in FPGA signal processing chain 
- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port

All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).
 2026-03-15 06:14:04 +02:00
NawfalMotii79 5fbe97fa5f Add files via upload 2026-03-09 00:17:39 +00:00