7 Commits

Author	SHA1	Message	Date
Jason	8d7b6e04a0	fix(rtl): force FIR adder tree to fabric to free 30 DSPs for FFT butterfly on 50T ... Add (* USE_DSP = "no" *) attribute to FIR lowpass adder tree registers (add_l1, add_l2, add_l3, accumulator_reg) to prevent Vivado from inferring DSP48E1 slices for pure addition operations. Each fir_lowpass_parallel_enhanced instance was using 47 DSPs (32 for multiply + 15 for the adder tree). The 15 adder-tree DSPs per instance (30 total for I/Q pair) performed only PCIN+A:B additions with no multiplier usage. On the XC7A50T with only 120 DSP48E1 slices, this caused 100% DSP utilization and forced FFT butterfly complex multipliers to spill into 18-level fabric carry chains (WNS=-1.103ns). Moving these 36-bit additions to fabric CARRY4 chains (~9 CARRY4 per add, ~2ns propagation) is well within the 10ns clock period and frees ~30 DSPs for the FFT engine to use native DSP48E1 multipliers. Regression: 23/23 FPGA tests PASS (attribute is synthesis-only).	2026-04-07 14:45:47 +03:00
Jason	ed6f79c6d3	FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache ... FIR: Add coeff_reg/mult_reg pipeline stages to fix 68 DPIP-1 + 35 DPOP-2 DRC warnings. Valid pipeline widened 7→9 bits (+2 cycle latency). Matched filter: Migrate input_buffer_i/q from register arrays to BRAM (~33K FF savings). Overlap-save uses register cache captured during ST_PROCESSING to avoid BRAM read/write conflicts during overlap copy. New ST_OVERLAP_COPY state writes cached tail samples back sequentially. Both changes pass 18/18 FPGA regression. Golden data regenerated for +2 FIR latency baseline.	2026-03-19 20:39:01 +02:00
Jason	d8a8532097	Convert CIC comb + FIR delay_line to sync reset for DSP48 absorption (Build 10) ... CIC: async→sync reset on decimation control, valid pipeline, and comb section. Added (* use_dsp = "yes" *) on comb[] to force DSP48E1 absorption of 28-bit subtracts (was 7-deep CARRY4, Build 9 critical path at WNS +0.128ns). Targets ~10 additional DSP48E1s. FIR: async→sync reset on delay_line block, enabling DSP48E1 AREG/BREG absorption. Targets elimination of ~2,522 DPIR-1 methodology warnings. 13/13 regression suites pass. Integration golden: 2048/2048 exact match.	2026-03-17 20:56:42 +02:00
Jason	1558f17d05	Convert async→sync reset on DSP/BRAM datapath registers for timing closure ... P1-CRITICAL: doppler_processor.v — split FSM into control (async reset) and BRAM/DSP datapath (sync reset) blocks. Fixes REQP-1839/1840 BRAM address register corruption risk; enables DSP48 absorption of window multipliers (mult_i/q). P1-CRITICAL: frequency_matched_filter.v — convert all 4 pipeline stages (input capture, multiply, add, saturate) from async to sync reset. Enables DSP48E1 absorption of complex multiplier registers. P1-HIGH: fir_lowpass.v — convert adder tree (L0-L4), output stage, and valid pipeline from async to sync reset. Fixes 856 DPOR-1 warnings (428 per FIR instance × 2 I/Q channels), enabling DSP48 absorption of the entire pipelined adder tree. Expected impact: eliminate ~1000 DRC warnings, improve WNS from +0.019ns by enabling Vivado to absorb hundreds of registers into DSP48E1/BRAM hard blocks. Full regression: 13/13 test suites pass (257+ assertions).	2026-03-17 20:11:13 +02:00
Jason	fd6094ee9e	Fix P0/P1 RTL bugs found during pre-hardware audit ... P0-1: nco_400m_enhanced.v — DSP48E1 OPMODE corrected from PCIN to P feedback (was routing stale cascade data into accumulator) P0-2: radar_receiver_final.v — removed same-clock CDC that corrupted ADC data path between ad9484_interface and DDC P1-5: fir_lowpass.v — fixed zero replication count in coefficient symmetric extension ({0{1'b0}} is empty, now uses explicit 0) Also updates .gitignore to exclude debug/scratch artifacts. All 30+ testbenches pass (unit, co-sim, integration).	2026-03-16 22:24:06 +02:00
Jason	00fbab6c9d	Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations) ... Complete FPGA timing closure across all clock domains after 9 iterative Vivado builds. WNS improved from -48.325ns to +0.018ns (107,886 endpoints). RTL fixes for 400 MHz timing: - NCO: 6-stage pipeline with DSP48E1 phase accumulator, registered LUT index (Fix D splits address decode from ROM read), distributed RAM - CIC: explicit DSP48E1 PCOUT->PCIN cascade for 5 integrator stages, CREG=1 on integrator_0 to eliminate fabric->DSP setup violation - DDC: 400 MHz reset synchronizer (async-assert/sync-deassert), active-high reset register for DSP48E1 RST ports, posedge output stage - FIR: 5-stage binary adder tree pipeline (7-cycle latency) - FFT: 5-cycle butterfly pipeline with registered twiddle index, XPM_MEMORY_TDPRAM for data storage - XDC: CDC false paths, async reset false paths, CIC comb multicycle paths Final Build 9 timing (all MET): adc_dco_p (400 MHz): WNS = +0.278ns clk_100m (100 MHz): WNS = +0.018ns clk_120m_dac (120 MHz): WNS = +0.992ns ft601_clk_in (100 MHz): WNS = +5.229ns Cross-domain (adc_dco_p->clk_100m): WNS = +7.105ns	2026-03-16 15:02:35 +02:00
NawfalMotii79	5fbe97fa5f	Add files via upload	2026-03-09 00:17:39 +00:00