4 Commits

Author	SHA1	Message	Date
Jason	0ae7b40ff0	Add TE0712/TE0701 split target with dedicated top, XDC, and build flow	2026-03-18 03:57:26 +02:00
Jason	12e63b750c	Fix ILA probe insertion script: deferred core creation, exact-path net resolution, Vivado 2025.2 MU_CNT minimum	2026-03-18 02:26:09 +02:00
Jason	f6877aab64	Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts ... - Rename latency_buffer_2159 -> latency_buffer (module + file + all refs) - Add CDC waivers for 5 verified false-positive criticals to XDC - Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains) - Add FPGA programming script (7-step flow with DONE pin verification) - Add ILA capture script (4 scenarios + health check, CSV export) - Add debug_ila.xdc with MARK_DEBUG fallback attributes - Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match	2026-03-18 01:28:42 +02:00
Jason	5fd632bc47	Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator ... CDC fixes across 6 RTL files based on post-implementation report_cdc analysis: - P0: sync stm32_mixers_enable and new_chirp_pulse to clk_120m via toggle CDC in radar_transmitter, add ft601 reset synchronizer and USB holding registers with proper edge detection in usb_data_interface - P1: add ASYNC_REG to edge_detector, convert new_chirp_frame to toggle CDC, fix USB valid edge detect to use fully-synced signal - P2: register Gray encoding in cdc_adc_to_processing source domain, sync ft601_txe and stm32_mixers_enable for status_reg in radar_system_top - Safety: add in_bin_count overflow guard in range_bin_decimator to prevent downstream BRAM corruption All 13 regression test suites pass (159 individual tests).	2026-03-17 13:48:47 +02:00