PLFM_RADAR

FlintyLemming/PLFM_RADAR

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Author	SHA1	Message	Date
Jason	0773001708	E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA) RTL fixes discovered via new end-to-end testbench: - plfm_chirp_controller: TX/RX mixer enables now mutually exclusive by FSM state (Fix #4), preventing simultaneous TX+RX activation - usb_data_interface: stream control reset default 3'b001 (range-only), added doppler/cfar data_pending sticky flags, write FSM triggers on range_valid only — eliminates startup deadlock (Fix #5) - radar_receiver_final: STM32 toggle signals wired through for mode-00 pass-through, dynamic frame detection via host_chirps_per_elev - radar_system_top: STM32 toggle signal wiring to receiver instance - chirp_memory_loader_param: explicit readmemh range for short chirp Test infrastructure: - New tb_system_e2e.v: 46 checks across 12 groups (reset, TX, safety, RX, USB R/W, CDC, beam scanning, reset recovery, stream control, latency budgets, watchdog) - tb_usb_data_interface: Tests 21/22/56 updated for data_pending architecture (preload flags, verify consumption instead of state) - tb_chirp_controller: mixer tests T7.1/T7.2 updated for Fix #4 - run_regression.sh: PASS/FAIL regex fixed to match only [PASS]/[FAIL] markers, added E2E test entry - Updated rx_final_doppler_out.csv golden data	2026-03-20 01:45:00 +02:00
Jason	94ffdb8f77	Add Phase 0 Vivado-style lint to regression runner, update golden data Adds two-layer lint pass (iverilog -Wall + custom static checks) that catches part-select OOB errors and case-without-default warnings before pushing to remote Vivado. Catches the exact Synth 8-524 class error that broke Build 18 initial attempt. Lint errors abort regression; warnings are advisory. Regenerated golden data for BRAM-migrated matched filter.	2026-03-19 21:19:07 +02:00
Jason	463ebef554	CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner - cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and data_valid_comb_pipe pipeline stages between integrator sampling and comb computation to break the critical path (matches remote 40cda0f) - radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard with pass-through assigns for iverilog compatibility - radar_system_tb.v: Convert generate_radar_echo function to task and move sin_lut declaration before task (iverilog declaration-order fix), add modular index clamping to prevent LUT out-of-bounds - run_regression.sh: Automated regression runner for all 18 FPGA testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail - .gitignore: Exclude .vvp, .vcd simulation artifacts	2026-03-19 11:31:46 +02:00

Author

SHA1

Message

Date

Jason

0773001708

E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)

RTL fixes discovered via new end-to-end testbench:
- plfm_chirp_controller: TX/RX mixer enables now mutually exclusive
  by FSM state (Fix #4), preventing simultaneous TX+RX activation
- usb_data_interface: stream control reset default 3'b001 (range-only),
  added doppler/cfar data_pending sticky flags, write FSM triggers on
  range_valid only — eliminates startup deadlock (Fix #5)
- radar_receiver_final: STM32 toggle signals wired through for mode-00
  pass-through, dynamic frame detection via host_chirps_per_elev
- radar_system_top: STM32 toggle signal wiring to receiver instance
- chirp_memory_loader_param: explicit readmemh range for short chirp

Test infrastructure:
- New tb_system_e2e.v: 46 checks across 12 groups (reset, TX, safety,
  RX, USB R/W, CDC, beam scanning, reset recovery, stream control,
  latency budgets, watchdog)
- tb_usb_data_interface: Tests 21/22/56 updated for data_pending
  architecture (preload flags, verify consumption instead of state)
- tb_chirp_controller: mixer tests T7.1/T7.2 updated for Fix #4
- run_regression.sh: PASS/FAIL regex fixed to match only [PASS]/[FAIL]
  markers, added E2E test entry
- Updated rx_final_doppler_out.csv golden data

2026-03-20 01:45:00 +02:00

Jason

94ffdb8f77

Add Phase 0 Vivado-style lint to regression runner, update golden data

Adds two-layer lint pass (iverilog -Wall + custom static checks) that
catches part-select OOB errors and case-without-default warnings before
pushing to remote Vivado. Catches the exact Synth 8-524 class error that
broke Build 18 initial attempt. Lint errors abort regression; warnings
are advisory. Regenerated golden data for BRAM-migrated matched filter.

2026-03-19 21:19:07 +02:00

Jason

463ebef554

CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner

- cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and
  data_valid_comb_pipe pipeline stages between integrator sampling and
  comb computation to break the critical path (matches remote 40cda0f)
- radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard
  with pass-through assigns for iverilog compatibility
- radar_system_tb.v: Convert generate_radar_echo function to task and
  move sin_lut declaration before task (iverilog declaration-order fix),
  add modular index clamping to prevent LUT out-of-bounds
- run_regression.sh: Automated regression runner for all 18 FPGA
  testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail
- .gitignore: Exclude *.vvp, *.vcd simulation artifacts

2026-03-19 11:31:46 +02:00

3 Commits