 Jason
|
f5a3394f23
|
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
Implement the 3 modules identified as missing during repo audit:
- matched_filter_processing_chain: behavioral FFT-based pulse compression
- range_bin_decimator: 1024→64 bin decimation with 3 modes + start_bin
- radar_mode_controller: 4-mode beam/chirp controller
Wire radar_mode_controller into radar_receiver_final.v to drive the
previously-undriven use_long_chirp and mc_new_* signals.
Implement start_bin functionality in range_bin_decimator (was dead code
in the original interface contract — now skips N input bins before
decimation for region-of-interest selection).
Add comprehensive testbenches with Tier 1 confidence improvements:
- Golden reference co-simulation (Python FFT → hex → bin comparison)
- Saturation boundary tests (0x7FFF / 0x8000 extremes)
- Reset mid-operation recovery tests
- Valid-gap / stall handling tests
- Mode switching and counter persistence tests
- Accumulator overflow stress tests
Test counts: matched_filter 40/40, range_bin_decimator 55/55,
radar_mode_controller 73/73 — all passing with iverilog -g2001.
|
2026-03-15 13:37:10 +02:00 |
|
|
Jason
|
558f49cd4a
|
Add 8 Verilog testbenches with full coverage (144/144 pass)
Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).
Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.
|
2026-03-15 06:14:11 +02:00 |
|
|
Jason
|
76183e2e95
|
Fix 6 RTL bugs in FPGA signal processing chain
- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port
All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).
|
2026-03-15 06:14:04 +02:00 |
|
 NawfalMotii79
|
7b6f93955f
|
Create cntrt.xdc
|
2026-03-10 02:42:15 +00:00 |
|
|
NawfalMotii79
|
a7e55c752f
|
Create usb_packet_analyzer.v
|
2026-03-10 01:36:04 +00:00 |
|
|
NawfalMotii79
|
220f2e0d0b
|
Create radar_system_tb.v
|
2026-03-10 01:35:26 +00:00 |
|
|
NawfalMotii79
|
45ad19184c
|
Add files via upload
|
2026-03-10 01:31:50 +00:00 |
|
|
NawfalMotii79
|
9d99a8e976
|
Add files via upload
|
2026-03-10 01:23:26 +00:00 |
|
|
NawfalMotii79
|
5fbe97fa5f
|
Add files via upload
|
2026-03-09 00:17:39 +00:00 |
|