 Jason
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00fbab6c9d
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Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)
Complete FPGA timing closure across all clock domains after 9 iterative
Vivado builds. WNS improved from -48.325ns to +0.018ns (107,886 endpoints).
RTL fixes for 400 MHz timing:
- NCO: 6-stage pipeline with DSP48E1 phase accumulator, registered LUT
index (Fix D splits address decode from ROM read), distributed RAM
- CIC: explicit DSP48E1 PCOUT->PCIN cascade for 5 integrator stages,
CREG=1 on integrator_0 to eliminate fabric->DSP setup violation
- DDC: 400 MHz reset synchronizer (async-assert/sync-deassert),
active-high reset register for DSP48E1 RST ports, posedge output stage
- FIR: 5-stage binary adder tree pipeline (7-cycle latency)
- FFT: 5-cycle butterfly pipeline with registered twiddle index,
XPM_MEMORY_TDPRAM for data storage
- XDC: CDC false paths, async reset false paths, CIC comb multicycle paths
Final Build 9 timing (all MET):
adc_dco_p (400 MHz): WNS = +0.278ns
clk_100m (100 MHz): WNS = +0.018ns
clk_120m_dac (120 MHz): WNS = +0.992ns
ft601_clk_in (100 MHz): WNS = +5.229ns
Cross-domain (adc_dco_p->clk_100m): WNS = +7.105ns
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2026-03-16 15:02:35 +02:00 |
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NawfalMotii79