7742b517b6
fix(fpga): implement 5 P0 invariant fixes with adversarial testbenches
...
Fixes 5 critical cross-layer invariant violations found during
system-level analysis. Each fix has a dedicated adversarial testbench
that actively tries to break the fix under race conditions, reset
mid-operation, overflow, and pathological input patterns.
RTL fixes:
- Fix #1 : Replace flawed cdc_adc_to_processing with Gray-coded async
FIFO (cdc_async_fifo) for DDC 400->100 MHz CDC path. Pre-fetch
show-ahead architecture with CDC-safe registered reads.
- Fix #2 : XOR toggle detection for mc_new_chirp in matched filter
(cross-clock-domain safe vs level-sensitive).
- Fix #3 : ST_WAIT_LISTEN state with configurable listen_delay to
prevent matched filter re-trigger during chirp dead time.
- Fix #4 : Overlap-save output trim in matched filter to suppress
circular convolution artifacts at segment boundaries.
- Fix #7 : Falling-edge frame_complete pulse in doppler_processor
(was stuck high, causing continuous AGC resets).
RTL cleanup:
- Refactor CDC synchronizer arrays from memory arrays to scalar regs
for explicit ASYNC_REG flop naming and synthesis constraint clarity.
Testbenches (70 checks total, all passing):
- tb_p0_async_fifo.v: 20 checks (fill, overflow, reset, streaming,
show-ahead capacity, pathological data patterns)
- tb_p0_mf_adversarial.v: 33 checks (toggle detection, listen state,
overlap trim, rapid chirp sequences, reset recovery)
- tb_p0_frame_pulse.v: 17 checks (pulse width, idle behavior,
processing duration sweep, regression vs old stuck-high bug)
Regression: 24/24 pass (--quick), 57/57 existing CDC tests pass.
Golden references updated for doppler output timing change.
2026-04-17 01:53:06 +05:45
fcf3999e39
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
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Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source
and destination clock domains use correctly-synchronized resets. Previously
cdc_chirp_counter's destination-side sync chain (100MHz) was reset by
sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings.
RTL changes:
- cdc_modules.v: split reset port, source logic uses src_reset_n,
destination sync chains + output logic use dst_reset_n
- radar_system_top.v: cdc_chirp_counter gets proper per-domain resets
- ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst)
- formal/fv_cdc_adc.v: updated wrapper for new port interface
Build 7 fixes (previously untouched):
- radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync
- latency_buffer_2159.v: BRAM read registration
- constraints: ft601 IOB -quiet fix
- tb_latency_buffer.v: updated for BRAM changes
Testbench hardening (tb_cdc_modules.v, +31 new assertions):
- A5-A7: split-domain reset tests (staggered deassertion, independent
dst reset while src active — catches the P0 bug class)
- A8: port connectivity (no X/Z on outputs)
- B7: cdc_single_bit port connectivity
- C6: cdc_handshake reset recovery + port connectivity
Full regression: 13/13 test suites pass (257 total assertions).
2026-03-17 19:38:09 +02:00
5fd632bc47
Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator
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CDC fixes across 6 RTL files based on post-implementation report_cdc analysis:
- P0: sync stm32_mixers_enable and new_chirp_pulse to clk_120m via toggle CDC
in radar_transmitter, add ft601 reset synchronizer and USB holding
registers with proper edge detection in usb_data_interface
- P1: add ASYNC_REG to edge_detector, convert new_chirp_frame to toggle CDC,
fix USB valid edge detect to use fully-synced signal
- P2: register Gray encoding in cdc_adc_to_processing source domain, sync
ft601_txe and stm32_mixers_enable for status_reg in radar_system_top
- Safety: add in_bin_count overflow guard in range_bin_decimator to prevent
downstream BRAM corruption
All 13 regression test suites pass (159 individual tests).
2026-03-17 13:48:47 +02:00
fb59e98737
Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs
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Formal verification (SymbiYosys + smtbmc/z3):
- cdc_single_bit: BMC PASS depth 80, cover PASS 3/3
- cdc_handshake: BMC PASS depth 100, cover PASS 4/4
- cdc_adc_to_processing: BMC PASS depth 80, cover PASS
- radar_mode_controller: BMC PASS depth 200, cover PASS 8/8
- range_bin_decimator: cover PASS 7/7, BMC running (step 61+)
- doppler_processor: cover running (step 133/150), BMC running (step 35+)
DUT bug fixes found by formal:
- doppler_processor: write_chirp_index overflow past CHIRPS_PER_FRAME-1
in S_ACCUMULATE frame-complete branch (reset to 0)
- doppler_processor: read_doppler_index unclamped prefetch in S_LOAD_FFT
causing OOB BRAM reads (clamped to DOPPLER_FFT_SIZE-1)
CDC fix (prior session, included):
- cdc_modules: async reset changed to sync reset on all CDC sync chains
to prevent metastability on reset deassertion
RTL changes for formal observability:
- Added ifdef FORMAL output ports to cdc_handshake (6), cdc_adc (2),
radar_mode_controller (2), range_bin_decimator (5), doppler_processor (11)
2026-03-17 12:47:22 +02:00
c983a3c705
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
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Phase 0+ timing optimization (attempts #13-22 + implementation):
NCO (nco_400m_enhanced.v):
- 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX
- DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain)
- Registered phase_inc_dithered to break cascaded 32-bit add path
DDC (ddc_400m.v):
- Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1)
- CEP=1, RSTP=!reset_n for proper pipeline control
- 3-stage dsp_valid_pipe for PREG=1 latency
- Behavioral sim model under ifdef SIMULATION for Icarus compatibility
CIC (cic_decimator_4x_enhanced.v):
- 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28
- Removed integrator/comb saturation (CIC uses wrapping arithmetic by design)
- Pipelined output saturation comparison
CDC/ASYNC_REG:
- ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v,
radar_system_top.v, usb_data_interface.v)
- Sync reset in generate blocks (cdc_modules.v)
Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints,
850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t.
All testbenches pass: 241/244 (3 known stub failures).
2026-03-16 01:02:07 +02:00
5fbe97fa5f
Add files via upload
2026-03-09 00:17:39 +00:00
Jason
NawfalMotii79