feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix
FPGA: - rx_gain_control.v rewritten: per-frame peak/saturation tracking, auto-shift AGC with attack/decay/holdoff, signed gain -7 to +7 - New registers 0x28-0x2C (agc_enable/target/attack/decay/holdoff) - status_words[4] carries AGC metrics (gain, peak, sat_count, enable) - DIG_5 GPIO outputs saturation flag for STM32 outer loop - Both USB interfaces (FT601 + FT2232H) updated with AGC status ports Timing fix (WNS +0.001ns -> +0.045ns, 45x improvement): - CIC max_fanout 4->16 on valid pipeline registers - +200ps setup uncertainty on 400MHz domain - ExtraNetDelay_high placement + AggressiveExplore routing GUI: - AGC opcodes + status parsing in radar_protocol.py - AGC control groups in both tkinter and V7 PyQt dashboards - 11 new AGC tests (103/103 GUI tests pass) Cross-layer: - AGC opcodes/defaults/status assertions added (29/29 pass) - contract_parser.py: fixed comment stripping in concat parser All tests green: 25 FPGA + 103 GUI + 29 cross-layer = 157 pass
This commit is contained in:
Jason
@@ -3,19 +3,32 @@
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/**
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* rx_gain_control.v
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*
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* Host-configurable digital gain control for the receive path.
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* Placed between DDC output (ddc_input_interface) and matched filter input.
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* Digital gain control with optional per-frame automatic gain control (AGC)
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* for the receive path. Placed between DDC output and matched filter input.
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*
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* Features:
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* - Bidirectional power-of-2 gain shift (arithmetic shift)
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* Manual mode (agc_enable=0):
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* - Uses host_gain_shift directly (backward-compatible, no behavioral change)
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* - gain_shift[3] = direction: 0 = left shift (amplify), 1 = right shift (attenuate)
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* - gain_shift[2:0] = amount: 0..7 bits
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* - Symmetric saturation to ±32767 on overflow (left shift only)
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* - Saturation counter: 8-bit, counts samples that clipped (wraps at 255)
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* - 1-cycle latency, valid-in/valid-out pipeline
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* - Zero-overhead pass-through when gain_shift == 0
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* - Symmetric saturation to ±32767 on overflow
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*
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* Intended insertion point in radar_receiver_final.v:
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* AGC mode (agc_enable=1):
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* - Per-frame automatic gain adjustment based on peak/saturation metrics
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* - Internal signed gain: -7 (max attenuation) to +7 (max amplification)
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* - On frame_boundary:
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* * If saturation detected: gain -= agc_attack (fast, immediate)
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* * Else if peak < target after holdoff frames: gain += agc_decay (slow)
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* * Else: hold current gain
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* - host_gain_shift serves as initial gain when AGC first enabled
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*
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* Status outputs (for readback via status_words):
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* - current_gain[3:0]: effective gain_shift encoding (manual or AGC)
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* - peak_magnitude[7:0]: per-frame peak |sample| (upper 8 bits of 15-bit value)
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* - saturation_count[7:0]: per-frame clipped sample count (capped at 255)
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*
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* Timing: 1-cycle data latency, valid-in/valid-out pipeline.
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*
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* Insertion point in radar_receiver_final.v:
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* ddc_input_interface → rx_gain_control → matched_filter_multi_segment
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*/
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@@ -28,27 +41,70 @@ module rx_gain_control (
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input wire signed [15:0] data_q_in,
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input wire valid_in,
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// Gain configuration (from host via USB command)
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// [3] = direction: 0=amplify (left shift), 1=attenuate (right shift)
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// [2:0] = shift amount: 0..7 bits
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// Host gain configuration (from USB command opcode 0x16)
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// [3]=direction: 0=amplify (left shift), 1=attenuate (right shift)
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// [2:0]=shift amount: 0..7 bits. Default 0x00 = pass-through.
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// In AGC mode: serves as initial gain on AGC enable transition.
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input wire [3:0] gain_shift,
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// AGC configuration inputs (from host via USB, opcodes 0x28-0x2C)
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input wire agc_enable, // 0x28: 0=manual gain, 1=auto AGC
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input wire [7:0] agc_target, // 0x29: target peak magnitude (unsigned, default 200)
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input wire [3:0] agc_attack, // 0x2A: attenuation step on clipping (default 1)
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input wire [3:0] agc_decay, // 0x2B: amplification step when weak (default 1)
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input wire [3:0] agc_holdoff, // 0x2C: frames to wait before gain-up (default 4)
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// Frame boundary pulse (1 clk cycle, from Doppler frame_complete)
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input wire frame_boundary,
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// Data output (to matched filter)
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output reg signed [15:0] data_i_out,
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output reg signed [15:0] data_q_out,
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output reg valid_out,
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// Diagnostics
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output reg [7:0] saturation_count // Number of clipped samples (wraps at 255)
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// Diagnostics / status readback
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output reg [7:0] saturation_count, // Per-frame clipped sample count (capped at 255)
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output reg [7:0] peak_magnitude, // Per-frame peak |sample| (upper 8 bits of 15-bit)
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output reg [3:0] current_gain // Current effective gain_shift (for status readback)
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);
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// Decompose gain_shift
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wire shift_right = gain_shift[3];
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wire [2:0] shift_amt = gain_shift[2:0];
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// =========================================================================
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// INTERNAL AGC STATE
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// =========================================================================
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// -------------------------------------------------------------------------
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// Combinational shift + saturation
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// -------------------------------------------------------------------------
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// Signed internal gain: -7 (max attenuation) to +7 (max amplification)
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// Stored as 4-bit signed (range -8..+7, clamped to -7..+7)
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reg signed [3:0] agc_gain;
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// Holdoff counter: counts frames without saturation before allowing gain-up
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reg [3:0] holdoff_counter;
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// Per-frame accumulators (running, reset on frame_boundary)
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reg [7:0] frame_sat_count; // Clipped samples this frame
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reg [14:0] frame_peak; // Peak |sample| this frame (15-bit unsigned)
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// Previous AGC enable state (for detecting 0→1 transition)
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reg agc_enable_prev;
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// =========================================================================
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// EFFECTIVE GAIN SELECTION
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// =========================================================================
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// Convert between signed internal gain and the gain_shift[3:0] encoding.
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// gain_shift[3]=0, [2:0]=N → amplify by N bits (internal gain = +N)
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// gain_shift[3]=1, [2:0]=N → attenuate by N bits (internal gain = -N)
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// Effective gain_shift used for the actual shift operation
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wire [3:0] effective_gain;
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assign effective_gain = agc_enable ? current_gain : gain_shift;
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// Decompose effective gain for shift logic
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wire shift_right = effective_gain[3];
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wire [2:0] shift_amt = effective_gain[2:0];
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// =========================================================================
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// COMBINATIONAL SHIFT + SATURATION
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// =========================================================================
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// Use wider intermediates to detect overflow on left shift.
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// 24 bits is enough: 16 + 7 shift = 23 significant bits max.
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@@ -69,26 +125,138 @@ wire signed [15:0] sat_i = overflow_i ? (shifted_i[23] ? -16'sd32768 : 16'sd3276
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wire signed [15:0] sat_q = overflow_q ? (shifted_q[23] ? -16'sd32768 : 16'sd32767)
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: shifted_q[15:0];
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// -------------------------------------------------------------------------
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// Registered output stage (1-cycle latency)
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// -------------------------------------------------------------------------
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// =========================================================================
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// PEAK MAGNITUDE TRACKING (combinational)
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// =========================================================================
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// Absolute value of signed 16-bit: flip sign bit if negative.
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// Result is 15-bit unsigned [0, 32767]. (We ignore -32768 → 32767 edge case.)
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wire [14:0] abs_i = data_i_in[15] ? (~data_i_in[14:0] + 15'd1) : data_i_in[14:0];
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wire [14:0] abs_q = data_q_in[15] ? (~data_q_in[14:0] + 15'd1) : data_q_in[14:0];
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wire [14:0] max_iq = (abs_i > abs_q) ? abs_i : abs_q;
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// =========================================================================
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// SIGNED GAIN ↔ GAIN_SHIFT ENCODING CONVERSION
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// =========================================================================
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// Convert signed agc_gain to gain_shift[3:0] encoding
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function [3:0] signed_to_encoding;
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input signed [3:0] g;
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begin
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if (g >= 0)
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signed_to_encoding = {1'b0, g[2:0]}; // amplify
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else
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signed_to_encoding = {1'b1, (~g[2:0]) + 3'd1}; // attenuate: -g
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end
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endfunction
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// Convert gain_shift[3:0] encoding to signed gain
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function signed [3:0] encoding_to_signed;
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input [3:0] enc;
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begin
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if (enc[3] == 1'b0)
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encoding_to_signed = {1'b0, enc[2:0]}; // +0..+7
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else
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encoding_to_signed = -$signed({1'b0, enc[2:0]}); // -1..-7
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end
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endfunction
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// =========================================================================
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// CLAMPING HELPER
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// =========================================================================
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// Clamp a wider signed value to [-7, +7]
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function signed [3:0] clamp_gain;
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input signed [4:0] val; // 5-bit to handle overflow from add
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begin
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if (val > 5'sd7)
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clamp_gain = 4'sd7;
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else if (val < -5'sd7)
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clamp_gain = -4'sd7;
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else
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clamp_gain = val[3:0];
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end
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endfunction
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// =========================================================================
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// REGISTERED OUTPUT + AGC STATE MACHINE
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// =========================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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// Data path
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data_i_out <= 16'sd0;
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data_q_out <= 16'sd0;
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valid_out <= 1'b0;
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// Status outputs
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saturation_count <= 8'd0;
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peak_magnitude <= 8'd0;
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current_gain <= 4'd0;
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// AGC internal state
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agc_gain <= 4'sd0;
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holdoff_counter <= 4'd0;
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frame_sat_count <= 8'd0;
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frame_peak <= 15'd0;
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agc_enable_prev <= 1'b0;
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end else begin
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valid_out <= valid_in;
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// Track AGC enable transitions
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agc_enable_prev <= agc_enable;
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// ---- Data pipeline (1-cycle latency) ----
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valid_out <= valid_in;
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if (valid_in) begin
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data_i_out <= sat_i;
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data_q_out <= sat_q;
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// Count clipped samples (either channel clipping counts as 1)
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if ((overflow_i || overflow_q) && (saturation_count != 8'hFF))
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saturation_count <= saturation_count + 8'd1;
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// Per-frame saturation counting
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if ((overflow_i || overflow_q) && (frame_sat_count != 8'hFF))
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frame_sat_count <= frame_sat_count + 8'd1;
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// Per-frame peak tracking (pre-gain, measures input signal level)
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if (max_iq > frame_peak)
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frame_peak <= max_iq;
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end
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// ---- Frame boundary: AGC update + metric snapshot ----
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if (frame_boundary) begin
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// Snapshot per-frame metrics to output registers
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saturation_count <= frame_sat_count;
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peak_magnitude <= frame_peak[14:7]; // Upper 8 bits of 15-bit peak
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// Reset per-frame accumulators for next frame
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frame_sat_count <= 8'd0;
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frame_peak <= 15'd0;
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if (agc_enable) begin
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// AGC auto-adjustment at frame boundary
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if (frame_sat_count > 8'd0) begin
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// Clipping detected: reduce gain immediately (attack)
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agc_gain <= clamp_gain($signed({1'b0, agc_gain}) -
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$signed({1'b0, agc_attack}));
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holdoff_counter <= agc_holdoff; // Reset holdoff
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end else if (frame_peak[14:7] < agc_target) begin
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// Signal too weak: increase gain after holdoff expires
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if (holdoff_counter == 4'd0) begin
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agc_gain <= clamp_gain($signed({1'b0, agc_gain}) +
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$signed({1'b0, agc_decay}));
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end else begin
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holdoff_counter <= holdoff_counter - 4'd1;
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end
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end else begin
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// Signal in good range, no saturation: hold gain
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// Reset holdoff so next weak frame has to wait again
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holdoff_counter <= agc_holdoff;
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end
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end
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end
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// ---- AGC enable transition: initialize from host gain ----
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if (agc_enable && !agc_enable_prev) begin
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agc_gain <= encoding_to_signed(gain_shift);
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holdoff_counter <= agc_holdoff;
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end
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// ---- Update current_gain output ----
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if (agc_enable)
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current_gain <= signed_to_encoding(agc_gain);
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else
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current_gain <= gain_shift;
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end
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end
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