Fix P0/P1 RTL bugs found during pre-hardware audit

P0-1: nco_400m_enhanced.v — DSP48E1 OPMODE corrected from PCIN to P
      feedback (was routing stale cascade data into accumulator)
P0-2: radar_receiver_final.v — removed same-clock CDC that corrupted
      ADC data path between ad9484_interface and DDC
P1-5: fir_lowpass.v — fixed zero replication count in coefficient
      symmetric extension ({0{1'b0}} is empty, now uses explicit 0)

Also updates .gitignore to exclude debug/scratch artifacts.

All 30+ testbenches pass (unit, co-sim, integration).

9_Firmware/9_2_FPGA/nco_400m_enhanced.v

@@ -217,7 +217,7 @@ DSP48E1 #(
     .D(25'b0),
     .CARRYIN(1'b0),
     // Control ports
-    .OPMODE(7'b0010011),         // Z=P (010), Y=0 (00), X=C_reg (11) → P = P + C
+    .OPMODE(7'b0101100),         // Z=P (010), Y=C (11), X=0 (00) → P = P + C
     .ALUMODE(4'b0000),           // Z + X + Y + CIN (standard add)
     .INMODE(5'b00000),
     .CARRYINSEL(3'b000),