Fix P0/P1 RTL bugs found during pre-hardware audit

P0-1: nco_400m_enhanced.v — DSP48E1 OPMODE corrected from PCIN to P
      feedback (was routing stale cascade data into accumulator)
P0-2: radar_receiver_final.v — removed same-clock CDC that corrupted
      ADC data path between ad9484_interface and DDC
P1-5: fir_lowpass.v — fixed zero replication count in coefficient
      symmetric extension ({0{1'b0}} is empty, now uses explicit 0)

Also updates .gitignore to exclude debug/scratch artifacts.

All 30+ testbenches pass (unit, co-sim, integration).

9_Firmware/9_2_FPGA/fir_lowpass.v

@@ -117,8 +117,11 @@ always @(posedge clk or negedge reset_n) begin
         end
     end else if (valid_pipe[0]) begin
         for (i = 0; i < 16; i = i + 1) begin
-            add_l0[i] <= {{(ACCUM_WIDTH-DATA_WIDTH-COEFF_WIDTH){mult_result[2*i][DATA_WIDTH+COEFF_WIDTH-1]}}, mult_result[2*i]} +
-                          {{(ACCUM_WIDTH-DATA_WIDTH-COEFF_WIDTH){mult_result[2*i+1][DATA_WIDTH+COEFF_WIDTH-1]}}, mult_result[2*i+1]};
+            // mult_result is (DATA_WIDTH + COEFF_WIDTH) = 36 bits = ACCUM_WIDTH,
+            // so no sign extension is needed. Direct assignment preserves the
+            // signed multiply result. (Fixes Vivado Synth 8-693 "zero replication
+            // count" warning from the original {0{sign_bit}} expression.)
+            add_l0[i] <= mult_result[2*i] + mult_result[2*i+1];
         end
     end
 end