Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source
and destination clock domains use correctly-synchronized resets. Previously
cdc_chirp_counter's destination-side sync chain (100MHz) was reset by
sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings.

RTL changes:
- cdc_modules.v: split reset port, source logic uses src_reset_n,
  destination sync chains + output logic use dst_reset_n
- radar_system_top.v: cdc_chirp_counter gets proper per-domain resets
- ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst)
- formal/fv_cdc_adc.v: updated wrapper for new port interface

Build 7 fixes (previously untouched):
- radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync
- latency_buffer_2159.v: BRAM read registration
- constraints: ft601 IOB -quiet fix
- tb_latency_buffer.v: updated for BRAM changes

Testbench hardening (tb_cdc_modules.v, +31 new assertions):
- A5-A7: split-domain reset tests (staggered deassertion, independent
  dst reset while src active — catches the P0 bug class)
- A8: port connectivity (no X/Z on outputs)
- B7: cdc_single_bit port connectivity
- C6: cdc_handshake reset recovery + port connectivity

Full regression: 13/13 test suites pass (257 total assertions).

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -255,13 +255,19 @@ cdc_single_bit #(.STAGES(2)) cdc_ft601_txe_status (
 // ============================================================================
 
 // CDC for chirp_counter: 6-bit multi-bit Gray-code synchronizer
+// Source domain is clk_120m_dac, so reset must be synchronized to that domain.
+// The cdc_adc_to_processing module uses synchronous reset internally, so
+// using sys_reset_120m_n (120m-synchronized) is correct for the source side.
+// The destination side will sample it synchronously on dst_clk, which at worst
+// delays reset deassertion by 1-2 cycles — acceptable for CDC reset.
 cdc_adc_to_processing #(
     .WIDTH(6),
     .STAGES(3)
 ) cdc_chirp_counter (
     .src_clk(clk_120m_dac_buf),
     .dst_clk(clk_100m_buf),
-    .reset_n(sys_reset_n),
+    .src_reset_n(sys_reset_120m_n),
+    .dst_reset_n(sys_reset_n),
     .src_data(tx_current_chirp),
     .src_valid(1'b1),           // Always valid — counter updates continuously
     .dst_data(tx_current_chirp_sync),
@@ -308,7 +314,8 @@ radar_transmitter tx_inst (
     // System Clocks
     .clk_100m(clk_100m_buf),
     .clk_120m_dac(clk_120m_dac_buf),
-    .reset_n(sys_reset_120m_n),  // Use 120 MHz-synchronized reset
+    .reset_n(sys_reset_120m_n),    // 120 MHz-synchronized reset for DAC-domain logic
+    .reset_100m_n(sys_reset_n),    // 100 MHz-synchronized reset for edge detectors/CDC
     
     // DAC Interface
     .dac_data(dac_data),