Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source
and destination clock domains use correctly-synchronized resets. Previously
cdc_chirp_counter's destination-side sync chain (100MHz) was reset by
sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings.

RTL changes:
- cdc_modules.v: split reset port, source logic uses src_reset_n,
  destination sync chains + output logic use dst_reset_n
- radar_system_top.v: cdc_chirp_counter gets proper per-domain resets
- ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst)
- formal/fv_cdc_adc.v: updated wrapper for new port interface

Build 7 fixes (previously untouched):
- radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync
- latency_buffer_2159.v: BRAM read registration
- constraints: ft601 IOB -quiet fix
- tb_latency_buffer.v: updated for BRAM changes

Testbench hardening (tb_cdc_modules.v, +31 new assertions):
- A5-A7: split-domain reset tests (staggered deassertion, independent
  dst reset while src active — catches the P0 bug class)
- A8: port connectivity (no X/Z on outputs)
- B7: cdc_single_bit port connectivity
- C6: cdc_handshake reset recovery + port connectivity

Full regression: 13/13 test suites pass (257 total assertions).

9_Firmware/9_2_FPGA/latency_buffer_2159.v

@@ -101,9 +101,28 @@ always @(posedge clk or negedge reset_n) begin
     end
 end
 
-// ========== OUTPUTS ==========
-assign data_out = bram[read_ptr];
-assign valid_out = valid_out_reg;
+// ========== BRAM READ (synchronous — required for Block RAM inference) ==========
+// Xilinx Block RAMs physically register the read output. An async read
+// (assign data_out = bram[addr]) forces Vivado to use distributed LUTRAM
+// instead, wasting ~704 LUTs. Registering the read adds 1 cycle of latency,
+// compensated by the valid pipeline stage below.
+reg [DATA_WIDTH-1:0] data_out_reg;
+
+always @(posedge clk) begin
+    data_out_reg <= bram[read_ptr];
+end
+
+// Pipeline valid_out_reg by 1 cycle to align with registered BRAM read
+reg valid_out_pipe;
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n)
+        valid_out_pipe <= 1'b0;
+    else
+        valid_out_pipe <= valid_out_reg;
+end
+
+assign data_out = data_out_reg;
+assign valid_out = valid_out_pipe;