Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source
and destination clock domains use correctly-synchronized resets. Previously
cdc_chirp_counter's destination-side sync chain (100MHz) was reset by
sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings.

RTL changes:
- cdc_modules.v: split reset port, source logic uses src_reset_n,
  destination sync chains + output logic use dst_reset_n
- radar_system_top.v: cdc_chirp_counter gets proper per-domain resets
- ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst)
- formal/fv_cdc_adc.v: updated wrapper for new port interface

Build 7 fixes (previously untouched):
- radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync
- latency_buffer_2159.v: BRAM read registration
- constraints: ft601 IOB -quiet fix
- tb_latency_buffer.v: updated for BRAM changes

Testbench hardening (tb_cdc_modules.v, +31 new assertions):
- A5-A7: split-domain reset tests (staggered deassertion, independent
  dst reset while src active — catches the P0 bug class)
- A8: port connectivity (no X/Z on outputs)
- B7: cdc_single_bit port connectivity
- C6: cdc_handshake reset recovery + port connectivity

Full regression: 13/13 test suites pass (257 total assertions).

9_Firmware/9_2_FPGA/cdc_modules.v

@@ -12,7 +12,8 @@ module cdc_adc_to_processing #(
 )(
     input wire src_clk,
     input wire dst_clk,
-    input wire reset_n,
+    input wire src_reset_n,
+    input wire dst_reset_n,
     input wire [WIDTH-1:0] src_data,
     input wire src_valid,
     output wire [WIDTH-1:0] dst_data,
@@ -59,7 +60,7 @@ module cdc_adc_to_processing #(
     // Gray encoding is registered in src_clk to avoid combinational logic
     // before the first synchronizer FF (fixes CDC-10 violations).
     always @(posedge src_clk) begin
-        if (!reset_n) begin
+        if (!src_reset_n) begin
             src_data_reg  <= 0;
             src_data_gray <= 0;
             src_toggle    <= 2'b00;
@@ -78,7 +79,7 @@ module cdc_adc_to_processing #(
     generate
         for (i = 0; i < STAGES; i = i + 1) begin : data_sync_chain
             always @(posedge dst_clk) begin
-                if (!reset_n) begin
+                if (!dst_reset_n) begin
                     dst_data_gray[i] <= 0;
                 end else begin
                     if (i == 0) begin
@@ -93,7 +94,7 @@ module cdc_adc_to_processing #(
         
         for (i = 0; i < STAGES; i = i + 1) begin : toggle_sync_chain
             always @(posedge dst_clk) begin
-                if (!reset_n) begin
+                if (!dst_reset_n) begin
                     dst_toggle_sync[i] <= 2'b00;
                 end else begin
                     if (i == 0) begin
@@ -108,7 +109,7 @@ module cdc_adc_to_processing #(
     
     // Detect new data — synchronous reset
     always @(posedge dst_clk) begin
-        if (!reset_n) begin
+        if (!dst_reset_n) begin
             dst_data_reg <= 0;
             dst_valid_reg <= 0;
             prev_dst_toggle <= 2'b00;