Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)

- Add cfar_ca.v: CA/GO/SO-CFAR with BRAM magnitude buffer, host-configurable
  guard cells, training cells, alpha multiplier, and mode selection
- Replace old threshold detector block in radar_system_top.v with cfar_ca
  instantiation; backward-compatible (cfar_enable defaults to 0)
- Add 5 new host registers: guard (0x21), train (0x22), alpha (0x23),
  mode (0x24), enable (0x25)
- Expose doppler_frame_done_out from radar_receiver_final for CFAR frame sync
- Add tb_cfar_ca.v standalone testbench (14 tests, 24 checks)
- Add Group 14 E2E tests: 13 checks covering range-mode (0x20) and all
  CFAR config registers (0x21-0x25) through full USB command path
- Update run_regression.sh with CFAR in lint, Phase 1, and integration compiles

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -48,7 +48,10 @@ module radar_receiver_final (
     // these to synchronize receiver processing with STM32-timed chirps.
     input wire stm32_new_chirp_rx,
     input wire stm32_new_elevation_rx,
-    input wire stm32_new_azimuth_rx
+    input wire stm32_new_azimuth_rx,
+
+    // CFAR integration: expose Doppler frame_complete to top level
+    output wire doppler_frame_done_out
 );
 
 // ========== INTERNAL SIGNALS ==========
@@ -91,6 +94,7 @@ wire doppler_spectrum_valid;
 wire [4:0] doppler_bin_out;
 wire doppler_processing;
 wire doppler_frame_done;
+assign doppler_frame_done_out = doppler_frame_done;
 
 // ========== RANGE BIN DECIMATOR SIGNALS ==========
 wire signed [15:0] decimated_range_i;