Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts

- Rename latency_buffer_2159 -> latency_buffer (module + file + all refs)
- Add CDC waivers for 5 verified false-positive criticals to XDC
- Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains)
- Add FPGA programming script (7-step flow with DONE pin verification)
- Add ILA capture script (4 scenarios + health check, CSV export)
- Add debug_ila.xdc with MARK_DEBUG fallback attributes
- Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match

9_Firmware/9_2_FPGA/tb/cosim/validate_mem_files.py

@@ -7,7 +7,7 @@ Checks:
   2. FFT twiddle files: bit-exact match against cos(2*pi*k/N) in Q15
   3. Long chirp .mem files: reverse-engineer parameters, check for chirp structure
   4. Short chirp .mem files: check length, value range, spectral content
-  5. latency_buffer_2159 LATENCY=3187 parameter validation
+   5. latency_buffer LATENCY=3187 parameter validation
 
 Usage:
     python3 validate_mem_files.py
@@ -479,8 +479,9 @@ def test_latency_buffer():
 
     # Check that the module name vs parameter is consistent
     print(f"  LATENCY parameter: {LATENCY}")
-    print(f"  Module name: latency_buffer_2159 (historical, actual LATENCY={LATENCY})")
-    warn("Module name 'latency_buffer_2159' is inconsistent with LATENCY=3187 parameter")
+    print(f"  Module name: latency_buffer (parameterized, LATENCY={LATENCY})")
+    # Module name was renamed from latency_buffer_2159 to latency_buffer
+    # to match the actual parameterized LATENCY value. No warning needed.
 
     # Validate address arithmetic won't overflow
     # read_ptr = (write_ptr - LATENCY) mod 4096