Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
- Rename latency_buffer_2159 -> latency_buffer (module + file + all refs) - Add CDC waivers for 5 verified false-positive criticals to XDC - Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains) - Add FPGA programming script (7-step flow with DONE pin verification) - Add ILA capture script (4 scenarios + health check, CSV export) - Add debug_ila.xdc with MARK_DEBUG fallback attributes - Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match
This commit is contained in:
Jason
@@ -0,0 +1,203 @@
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################################################################################
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# debug_ila.xdc
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#
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# AERIS-10 Radar FPGA — mark_debug Constraints for ILA Probe Signals
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# Target: XC7A200T-2FBG484I
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#
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# ALTERNATIVE APPROACH: If the post-synthesis ILA insertion script
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# (insert_ila_probes.tcl) encounters net-name resolution issues, add this
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# XDC to the Vivado project *before* synthesis. The mark_debug attributes
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# will preserve the nets through optimization and make them available for
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# ILA insertion in the Setup Debug wizard or via TCL.
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#
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# Usage:
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# 1. Add this file to the Vivado project as a constraint source
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# 2. Re-run synthesis (nets will be preserved with MARK_DEBUG)
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# 3. Use Vivado GUI: Flow > Set Up Debug, or run insert_ila_probes.tcl
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#
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# NOTE: mark_debug must be applied to RTL-level signal names. After
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# synthesis, Vivado will propagate the attribute to the corresponding
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# netlist nets regardless of renaming or flattening.
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################################################################################
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# ==============================================================================
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# ILA 0 — ADC Capture (400 MHz domain)
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#
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# Raw ADC samples from the AD9484 CMOS interface inside the receiver.
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# 8-bit data bus + valid strobe. Clocked at 400 MHz (adc_dco_p derived).
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# ==============================================================================
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# ADC raw data bus [7:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_data_cmos[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_data_cmos[1]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_data_cmos[2]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_data_cmos[3]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_data_cmos[4]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_data_cmos[5]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_data_cmos[6]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_data_cmos[7]}]
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# ADC data valid
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set_property MARK_DEBUG true [get_nets {rx_inst/adc/adc_valid}]
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# ==============================================================================
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# ILA 1 — DDC Output (100 MHz domain)
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#
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# Digital down-converter baseband I/Q outputs after CIC + FIR decimation.
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# 18-bit I + 18-bit Q + valid strobe. Clocked at 100 MHz (clk_100m_buf).
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# ==============================================================================
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# DDC I-channel [17:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[1]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[2]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[3]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[4]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[5]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[6]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[7]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[8]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[9]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[10]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[11]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[12]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[13]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[14]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[15]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[16]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_i[17]}]
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# DDC Q-channel [17:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[1]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[2]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[3]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[4]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[5]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[6]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[7]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[8]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[9]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[10]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[11]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[12]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[13]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[14]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[15]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[16]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_out_q[17]}]
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# DDC valid strobe
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set_property MARK_DEBUG true [get_nets {rx_inst/ddc_valid_i}]
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# ==============================================================================
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# ILA 2 — Matched Filter Output (100 MHz domain)
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#
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# Pulse-compression output from the multi-segment matched filter.
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# 16-bit I + 16-bit Q + valid + 2-bit segment index.
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# ==============================================================================
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# Matched filter I-channel [15:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[1]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[2]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[3]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[4]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[5]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[6]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[7]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[8]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[9]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[10]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[11]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[12]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[13]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[14]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_i_w[15]}]
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# Matched filter Q-channel [15:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[1]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[2]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[3]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[4]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[5]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[6]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[7]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[8]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[9]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[10]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[11]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[12]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[13]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[14]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_q_w[15]}]
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# Matched filter valid
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/pc_valid_w}]
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# Matched filter segment request [1:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/segment_request[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/mf_dual/segment_request[1]}]
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# ==============================================================================
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# ILA 3 — Doppler Processor Output (100 MHz domain)
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#
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# Range-Doppler map output from FFT-based Doppler processor.
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# 32-bit spectrum + valid + 5-bit Doppler bin + 6-bit range bin + frame sync.
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# ==============================================================================
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# Doppler output spectrum [31:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[1]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[2]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[3]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[4]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[5]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[6]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[7]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[8]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[9]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[10]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[11]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[12]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[13]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[14]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[15]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[16]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[17]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[18]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[19]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[20]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[21]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[22]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[23]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[24]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[25]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[26]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[27]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[28]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[29]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[30]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_output[31]}]
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# Doppler valid
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_valid}]
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# Doppler bin index [4:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_bin[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_bin[1]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_bin[2]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_bin[3]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/doppler_bin[4]}]
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# Range bin index [5:0]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/range_bin[0]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/range_bin[1]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/range_bin[2]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/range_bin[3]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/range_bin[4]}]
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set_property MARK_DEBUG true [get_nets {rx_inst/doppler_proc/range_bin[5]}]
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# Frame synchronization pulse
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set_property MARK_DEBUG true [get_nets {rx_inst/new_frame_pulse}]
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@@ -696,6 +696,53 @@ set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst
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# -from [get_cells -hierarchical -filter {NAME =~ *cic_*/integrator_*_dsp}] \
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# -to [get_cells -hierarchical -filter {NAME =~ *cic_*/integrator_*_dsp}]
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# ============================================================================
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# CDC WAIVERS — Verified False Positives (Build 13 Freeze Candidate)
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# ============================================================================
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# These 5 CDC critical warnings were analyzed during pre-hardware audit.
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# All are structurally safe and do not represent real metastability risks.
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# See project documentation for detailed justification of each waiver.
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#
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# Waiver 1: CDC-11 — 100MHz reset_sync → 400MHz ADC reset synchronizer
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# Standard async-assert/sync-deassert pattern. ASYNC_REG is applied on
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# the destination synchronizer chain. Reset is held for many source cycles.
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create_waiver -type CDC -id CDC-11 \
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-from [get_pins -quiet -hierarchical -filter {NAME =~ *reset_sync_reg[1]/C}] \
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-to [get_pins -quiet -hierarchical -filter {NAME =~ *rx_inst/adc/reset_sync_400m_reg[0]/CLR}] \
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-description "Reset synchronizer 100M->400M: async-assert/sync-deassert, ASYNC_REG applied"
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# Waiver 2: CDC-7 — 100MHz reset_sync → DDC active-high reset PRE
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# Active-high derived reset uses PRE (preset). PRE is the safe async
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# direction for this reset polarity. Parent chain has ASYNC_REG.
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create_waiver -type CDC -id CDC-7 \
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-from [get_pins -quiet -hierarchical -filter {NAME =~ *reset_sync_reg[1]/C}] \
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-to [get_pins -quiet -hierarchical -filter {NAME =~ *rx_inst/ddc/reset_400m_reg/PRE}] \
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-description "DDC active-high reset via PRE: safe async direction, ASYNC_REG on parent chain"
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# Waiver 3: CDC-11 — 100MHz reset_sync → DDC 400MHz reset synchronizer
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# Same pattern as Waiver 1, different destination module (DDC vs ADC).
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create_waiver -type CDC -id CDC-11 \
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-from [get_pins -quiet -hierarchical -filter {NAME =~ *reset_sync_reg[1]/C}] \
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-to [get_pins -quiet -hierarchical -filter {NAME =~ *rx_inst/ddc/reset_sync_400m_reg[0]/CLR}] \
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-description "Reset synchronizer 100M->400M in DDC: async-assert/sync-deassert, ASYNC_REG applied"
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# Waiver 4: CDC-11 — doppler_valid fan-out to USB doppler_valid_sync
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# Single rx_doppler_valid register fans out to two independent 2-stage
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# synchronizers in usb_data_interface. Both sync chains have ASYNC_REG.
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# The fan-out is covered by set_false_path (clk_100m ↔ ft601_clk_in).
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create_waiver -type CDC -id CDC-11 \
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-from [get_pins -quiet -hierarchical -filter {NAME =~ *doppler_valid_reg/C}] \
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-to [get_pins -quiet -hierarchical -filter {NAME =~ *usb_inst/doppler_valid_sync_reg[0]/D}] \
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-description "doppler_valid CDC fan-out to USB sync chain 1: ASYNC_REG + false_path applied"
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# Waiver 5: CDC-11 — doppler_valid fan-out to USB range_valid_sync
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# Second fan-out endpoint of the same doppler_valid signal. Same
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# justification as Waiver 4.
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create_waiver -type CDC -id CDC-11 \
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-from [get_pins -quiet -hierarchical -filter {NAME =~ *doppler_valid_reg/C}] \
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-to [get_pins -quiet -hierarchical -filter {NAME =~ *usb_inst/range_valid_sync_reg[0]/D}] \
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-description "doppler_valid CDC fan-out to USB sync chain 2: ASYNC_REG + false_path applied"
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# ============================================================================
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# END OF CONSTRAINTS
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# ============================================================================
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