Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

Implement the 3 modules identified as missing during repo audit:
- matched_filter_processing_chain: behavioral FFT-based pulse compression
- range_bin_decimator: 1024→64 bin decimation with 3 modes + start_bin
- radar_mode_controller: 4-mode beam/chirp controller

Wire radar_mode_controller into radar_receiver_final.v to drive the
previously-undriven use_long_chirp and mc_new_* signals.

Implement start_bin functionality in range_bin_decimator (was dead code
in the original interface contract — now skips N input bins before
decimation for region-of-interest selection).

Add comprehensive testbenches with Tier 1 confidence improvements:
- Golden reference co-simulation (Python FFT → hex → bin comparison)
- Saturation boundary tests (0x7FFF / 0x8000 extremes)
- Reset mid-operation recovery tests
- Valid-gap / stall handling tests
- Mode switching and counter persistence tests
- Accumulator overflow stress tests

Test counts: matched_filter 40/40, range_bin_decimator 55/55,
radar_mode_controller 73/73 — all passing with iverilog -g2001.

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -27,6 +27,11 @@ wire chirp_start;
 wire azimuth_change;
 wire elevation_change;
 
+// Mode controller outputs → matched_filter_multi_segment
+wire mc_new_chirp;
+wire mc_new_elevation;
+wire mc_new_azimuth;
+
 wire [1:0] segment_request;
 wire mem_request;
 wire [15:0] ref_i, ref_q;
@@ -58,7 +63,35 @@ wire signed [15:0] decimated_range_q;
 wire decimated_range_valid;
 wire [5:0] decimated_range_bin;
 
+// ========== RADAR MODE CONTROLLER SIGNALS ==========
+wire rmc_scanning;
+wire rmc_scan_complete;
+wire [5:0] rmc_chirp_count;
+wire [5:0] rmc_elevation_count;
+wire [5:0] rmc_azimuth_count;
+
 // ========== MODULE INSTANTIATIONS ==========
+
+// 0. Radar Mode Controller — drives chirp/elevation/azimuth timing signals
+//    Default mode: auto-scan (2'b01). Change to 2'b00 for STM32 pass-through.
+radar_mode_controller rmc (
+    .clk(clk),
+    .reset_n(reset_n),
+    .mode(2'b01),                     // Auto-scan mode
+    .stm32_new_chirp(1'b0),           // Unused in auto mode
+    .stm32_new_elevation(1'b0),       // Unused in auto mode
+    .stm32_new_azimuth(1'b0),         // Unused in auto mode
+    .trigger(1'b0),                   // Unused in auto mode
+    .use_long_chirp(use_long_chirp),
+    .mc_new_chirp(mc_new_chirp),
+    .mc_new_elevation(mc_new_elevation),
+    .mc_new_azimuth(mc_new_azimuth),
+    .chirp_count(rmc_chirp_count),
+    .elevation_count(rmc_elevation_count),
+    .azimuth_count(rmc_azimuth_count),
+    .scanning(rmc_scanning),
+    .scan_complete(rmc_scan_complete)
+);
 reg clk_400m;
 
 lvds_to_cmos_400m clk_400m_inst(