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Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

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Resolves all synthesis errors across attempts 3-11, achieving clean
Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs).

radar_receiver_final.v:
- reg clk_400m -> wire; output reg -> output wire (x4)
- Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m
- Remove duplicate IBUFDS lvds_to_cmos_400m instantiation
- Remove non-existent ref_i/ref_q port connections on matched filter
- Connect adc_dco_bufg as 400MHz clock source

ad9484_interface_400m.v:
- Add adc_dco_bufg output port with BUFG instance
- Route all internal logic through buffered DCO clock

cic_decimator_4x_enhanced.v:
- Move reset_monitors handling inside else branch (fixes Vivado
  ambiguous clock error in both integrator and comb always blocks)
- Add separate comb_overflow_latched/comb_saturation_detected regs
  to eliminate multi-driven nets between integrator and comb blocks
- Remove standalone always @(posedge reset_monitors) block
- Add output_counter to async reset branch

matched_filter_processing_chain.v:
- Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION
- Add synthesis stub tying outputs to safe defaults

chirp_memory_loader_param.v:
- Replace hardcoded Windows paths with relative filenames for all
  10 $readmem default parameters

latency_buffer_2159.v:
- Split single always block into separate BRAM write (synchronous
  only) and control logic (with async reset) blocks
- Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset

xfft_32.v (NEW):
- Synthesis stub for Xilinx 32-point FFT IP core
- AXI-Stream interface with pass-through and 1-cycle latency
- Placeholder until real xfft IP is generated
This commit is contained in:
Jason
2026-03-15 17:37:59 +02:00
parent c871281f1e
commit eefaf94e9e
7 changed files with 407 additions and 321 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/ad9484_interface_400m.v
+12 -3
View File
@@ -11,7 +11,8 @@ module ad9484_interface_400m (
// Output at 400MHz domain
output wire [7:0] adc_data_400m, // ADC data at 400MHz
output wire adc_data_valid_400m // Valid at 400MHz
output wire adc_data_valid_400m, // Valid at 400MHz
output wire adc_dco_bufg // Buffered 400MHz DCO clock for downstream use
);
// LVDS to single-ended conversion
@@ -43,6 +44,14 @@ IBUFDS #(
.IB(adc_dco_n)
);
// Global clock buffer for DCO — used as 400MHz clock throughout receiver
wire adc_dco_buffered;
BUFG bufg_dco (
.I(adc_dco),
.O(adc_dco_buffered)
);
assign adc_dco_bufg = adc_dco_buffered;
// IDDR for capturing DDR data
wire [7:0] adc_data_rise; // Data on rising edge
wire [7:0] adc_data_fall; // Data on falling edge
@@ -58,7 +67,7 @@ generate
) iddr_inst (
.Q1(adc_data_rise[j]), // Rising edge data
.Q2(adc_data_fall[j]), // Falling edge data
.C(adc_dco), // 400MHz DCO
.C(adc_dco_buffered), // 400MHz DCO (buffered)
.CE(1'b1),
.D(adc_data[j]),
.R(1'b0),
@@ -72,7 +81,7 @@ reg [7:0] adc_data_400m_reg;
reg adc_data_valid_400m_reg;
reg dco_phase;
always @(posedge adc_dco or negedge reset_n) begin
always @(posedge adc_dco_buffered or negedge reset_n) begin
if (!reset_n) begin
adc_data_400m_reg <= 8'b0;
adc_data_valid_400m_reg <= 1'b0;
9_Firmware/9_2_FPGA/chirp_memory_loader_param.v
+10 -10
View File
@@ -1,15 +1,15 @@
`timescale 1ns / 1ps
module chirp_memory_loader_param #(
parameter LONG_I_FILE_SEG0 = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/long_chirp_seg0_i.mem",
parameter LONG_Q_FILE_SEG0 = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/long_chirp_seg0_q.mem",
parameter LONG_I_FILE_SEG1 = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/long_chirp_seg1_i.mem",
parameter LONG_Q_FILE_SEG1 = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/long_chirp_seg1_q.mem",
parameter LONG_I_FILE_SEG2 = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/long_chirp_seg2_i.mem",
parameter LONG_Q_FILE_SEG2 = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/long_chirp_seg2_q.mem",
parameter LONG_I_FILE_SEG3 = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/long_chirp_seg3_i.mem",
parameter LONG_Q_FILE_SEG3 = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/long_chirp_seg3_q.mem",
parameter SHORT_I_FILE = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/short_chirp_i.mem",
parameter SHORT_Q_FILE = "C:/Users/dell/Desktop/ASUS/RADAR_V5/Firmware/FPGA/PLFM_RADAR_Xilinx_ISE_V2/Python/mem_files/fpga_mem_files/short_chirp_q.mem",
parameter LONG_I_FILE_SEG0 = "long_chirp_seg0_i.mem",
parameter LONG_Q_FILE_SEG0 = "long_chirp_seg0_q.mem",
parameter LONG_I_FILE_SEG1 = "long_chirp_seg1_i.mem",
parameter LONG_Q_FILE_SEG1 = "long_chirp_seg1_q.mem",
parameter LONG_I_FILE_SEG2 = "long_chirp_seg2_i.mem",
parameter LONG_Q_FILE_SEG2 = "long_chirp_seg2_q.mem",
parameter LONG_I_FILE_SEG3 = "long_chirp_seg3_i.mem",
parameter LONG_Q_FILE_SEG3 = "long_chirp_seg3_q.mem",
parameter SHORT_I_FILE = "short_chirp_i.mem",
parameter SHORT_Q_FILE = "short_chirp_q.mem",
parameter DEBUG = 1
)(
input wire clk,
9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
+53 -59
View File
@@ -33,6 +33,11 @@ reg overflow_latched; // Latched overflow indicator
reg [7:0] saturation_event_count;
reg [31:0] sample_count;
// Comb-stage saturation flags (separate from integrator block to avoid multi-driven nets)
reg comb_overflow_latched;
reg comb_saturation_detected;
reg [7:0] comb_saturation_event_count;
// Temporary signals for calculations
reg signed [35:0] abs_integrator_value;
reg signed [35:0] temp_scaled_output;
@@ -65,6 +70,9 @@ initial begin
abs_integrator_value = 0;
temp_scaled_output = 0;
temp_output = 0;
comb_overflow_latched = 0;
comb_saturation_detected = 0;
comb_saturation_event_count = 0;
end
// Enhanced integrator section with proper saturation monitoring
@@ -75,19 +83,27 @@ always @(posedge clk or negedge reset_n) begin
end
decimation_counter <= 0;
data_valid_delayed <= 0;
data_valid_comb <= 0;
max_integrator_value <= 0;
overflow_detected <= 0;
sample_count <= 0;
abs_integrator_value <= 0;
if (reset_monitors) begin
overflow_latched <= 0;
saturation_detected <= 0;
saturation_event_count <= 0;
max_value_monitor <= 0;
output_counter <= 0;
end else begin
// Monitor control - clear latched saturation on reset_monitors
// (must be inside else branch so Vivado sees a clean async-reset FF template)
if (reset_monitors) begin
overflow_latched <= 0;
saturation_detected <= 0;
max_integrator_value <= 0;
max_value_monitor <= 0;
saturation_event_count <= 0;
end
end else if (data_valid) begin
if (data_valid) begin
sample_count <= sample_count + 1;
// First integrator stage with enhanced saturation detection
@@ -120,7 +136,7 @@ always @(posedge clk or negedge reset_n) begin
// Track maximum integrator value for gain monitoring (absolute value)
if (abs_integrator_value > max_integrator_value) begin
max_integrator_value <= abs_integrator_value;
max_value_monitor <= abs_integrator_value[31:24]; // Fixed: use the calculated absolute value
max_value_monitor <= abs_integrator_value[31:24];
end
// Remaining integrator stages with saturation protection
@@ -145,14 +161,6 @@ always @(posedge clk or negedge reset_n) begin
decimation_counter <= 0;
data_valid_delayed <= 1;
output_counter <= output_counter + 1;
/*// Debug output for first few samples
if (output_counter < 10) begin
$display("CIC_DECIM: sample=%0d, integrator[%0d]=%h, max_val=%h, sat=%b",
output_counter, STAGES-1, integrator[STAGES-1],
max_integrator_value, saturation_detected);
end
*/
end else begin
decimation_counter <= decimation_counter + 1;
data_valid_delayed <= 0;
@@ -161,14 +169,6 @@ always @(posedge clk or negedge reset_n) begin
data_valid_delayed <= 0;
overflow_detected <= 1'b0; // Clear immediate detection when no data
end
// Monitor control - clear latched saturation on reset_monitors
if (reset_monitors) begin
overflow_latched <= 0;
saturation_detected <= 0;
max_integrator_value <= 0;
max_value_monitor <= 0;
saturation_event_count <= 0;
end
end
@@ -194,19 +194,31 @@ always @(posedge clk or negedge reset_n) begin
data_out_valid <= 0;
temp_scaled_output <= 0;
temp_output <= 0;
end else if (data_valid_comb) begin
comb_overflow_latched <= 0;
comb_saturation_detected <= 0;
comb_saturation_event_count <= 0;
end else begin
// Monitor control - clear latched comb saturation on reset_monitors
// (inside else branch so Vivado sees clean async-reset FF template)
if (reset_monitors) begin
comb_overflow_latched <= 0;
comb_saturation_detected <= 0;
comb_saturation_event_count <= 0;
end
if (data_valid_comb) begin
// Enhanced comb processing with saturation check
for (i = 0; i < STAGES; i = i + 1) begin
if (i == 0) begin
// Check for comb stage saturation
if (integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1] > (2**35 - 1)) begin
comb[0] <= (2**35 - 1);
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
end else if (integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1] < -(2**35)) begin
comb[0] <= -(2**35);
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
end else begin
comb[0] <= integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1];
end
@@ -220,12 +232,12 @@ always @(posedge clk or negedge reset_n) begin
// Check for comb stage saturation
if (comb[i-1] - comb_delay[i][COMB_DELAY-1] > (2**35 - 1)) begin
comb[i] <= (2**35 - 1);
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
end else if (comb[i-1] - comb_delay[i][COMB_DELAY-1] < -(2**35)) begin
comb[i] <= -(2**35);
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
end else begin
comb[i] <= comb[i-1] - comb_delay[i][COMB_DELAY-1];
end
@@ -246,47 +258,36 @@ always @(posedge clk or negedge reset_n) begin
temp_output <= temp_scaled_output[17:0];
// FIXED: Proper saturation detection for 18-bit signed range
// Check if the 18-bit truncated value matches the intended value
if (temp_scaled_output > 131071) begin // 2^17 - 1
data_out <= 131071;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
comb_saturation_event_count <= comb_saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Positive saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d",
comb[STAGES-1], temp_scaled_output, temp_output, 131071);
`endif
end else if (temp_scaled_output < -131072) begin // -2^17
data_out <= -131072;
overflow_latched <= 1'b1;
saturation_detected <= 1'b1;
saturation_event_count <= saturation_event_count + 1;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
comb_saturation_event_count <= comb_saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Negative saturation, raw=%h, scaled=%h, temp_out=%d, final_out=%d",
comb[STAGES-1], temp_scaled_output, temp_output, -131072);
`endif
end else begin
// FIXED: Use the properly truncated 18-bit value
data_out <= temp_output;
overflow_latched <= 1'b0;
saturation_detected <= 1'b0;
if (output_counter < 20) begin
//$display("CIC_OUTPUT_GOOD: raw=%h, scaled=%h, temp_out=%d, final_out=%d",
// comb[STAGES-1], temp_scaled_output, temp_output, data_out);
end
comb_overflow_latched <= 1'b0;
comb_saturation_detected <= 1'b0;
end
data_out_valid <= 1;
// Debug output for first samples
if (output_counter < 10) begin
// $display("CIC_DEBUG: sample=%0d, raw=%h, scaled=%h, out=%d, sat=%b",
// output_counter, comb[STAGES-1], temp_scaled_output, data_out, saturation_detected);
end
end else begin
data_out_valid <= 0;
end
end
end
// Continuous monitoring of saturation status
`ifdef SIMULATION
@@ -297,14 +298,7 @@ always @(posedge clk) begin
end
`endif
// Clear saturation on external reset
always @(posedge reset_monitors) begin
if (reset_monitors) begin
overflow_latched <= 0;
saturation_detected <= 0;
saturation_event_count <= 0;
//$display("CIC_MONITORS: All monitors reset");
end
end
// Clear saturation on external reset — handled in integrator always block
// (lines 165-172, using synchronous check of reset_monitors)
endmodule
9_Firmware/9_2_FPGA/latency_buffer_2159.v
+11 -8
View File
@@ -39,7 +39,17 @@ initial begin
buffer_has_data = 0;
end
// ========== FIXED STATE MACHINE ==========
// ========== BRAM WRITE (synchronous only, no async reset) ==========
// Xilinx Block RAMs do not support asynchronous resets.
// Separating the BRAM write into its own always block avoids Synth 8-3391.
// The initial block above handles power-on initialization for FPGA.
always @(posedge clk) begin
if (valid_in) begin
bram[write_ptr] <= data_in;
end
end
// ========== CONTROL LOGIC (with async reset) ==========
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
write_ptr <= 0;
@@ -53,9 +63,6 @@ always @(posedge clk or negedge reset_n) begin
// ===== WRITE SIDE =====
if (valid_in) begin
// Store data
bram[write_ptr] <= data_in;
// Increment write pointer (wrap at 4095)
if (write_ptr == 4095) begin
write_ptr <= 0;
@@ -70,7 +77,6 @@ always @(posedge clk or negedge reset_n) begin
// When we've written LATENCY samples, buffer is "primed"
if (delay_counter == LATENCY - 1) begin
buffer_has_data <= 1'b1;
// $display("[LAT_BUF] Buffer now has %d samples (primed)", LATENCY);
end
end
end
@@ -91,9 +97,6 @@ always @(posedge clk or negedge reset_n) begin
// Output is valid
valid_out_reg <= 1'b1;
//$display("[LAT_BUF] Reading: write_ptr=%d, read_ptr=%d, data=%h",
// write_ptr, read_ptr, bram[read_ptr]);
end
end
end
9_Firmware/9_2_FPGA/matched_filter_processing_chain.v
+18
View File
@@ -62,6 +62,7 @@ module matched_filter_processing_chain (
output wire [3:0] chain_state
);
`ifdef SIMULATION
// ============================================================================
// PARAMETERS
// ============================================================================
@@ -526,4 +527,21 @@ initial begin
end
end
`else
// ============================================================================
// SYNTHESIS STUB
// ============================================================================
// The behavioral FFT implementation above uses $cos/$sin/$rtoi (non-
// synthesizable). For real hardware, replace this stub with Xilinx xfft
// IP cores or a synthesizable pipelined FFT. The stub ties outputs to
// safe defaults so the rest of the design can be synthesized and verified.
// ============================================================================
assign range_profile_i = 16'd0;
assign range_profile_q = 16'd0;
assign range_profile_valid = 1'b0;
assign chain_state = 4'd0; // permanently IDLE
`endif
endmodule
9_Firmware/9_2_FPGA/radar_receiver_final.v
+21 -30
View File
@@ -14,10 +14,10 @@ module radar_receiver_final (
// Chirp counter from transmitter (for frame sync and matched filter)
input wire [5:0] chirp_counter,
output reg [31:0] doppler_output,
output reg doppler_valid,
output reg [4:0] doppler_bin,
output reg [5:0] range_bin
output wire [31:0] doppler_output,
output wire doppler_valid,
output wire [4:0] doppler_bin,
output wire [5:0] range_bin
);
// ========== INTERNAL SIGNALS ==========
@@ -53,7 +53,6 @@ wire new_chirp_frame;
wire [31:0] doppler_spectrum;
wire doppler_spectrum_valid;
wire [4:0] doppler_bin_out;
wire [5:0] doppler_range_bin_out;
wire doppler_processing;
wire doppler_frame_done;
@@ -92,46 +91,41 @@ radar_mode_controller rmc (
.scanning(rmc_scanning),
.scan_complete(rmc_scan_complete)
);
reg clk_400m;
wire clk_400m;
lvds_to_cmos_400m clk_400m_inst(
// ADC Physical Interface (LVDS Inputs)
.clk_400m_p(adc_dco_p), // Data Clock Output P (400MHz LVDS, 2.5V)
.clk_400m_n(adc_dco_n), // Data Clock Output N (400MHz LVDS, 2.5V)
.reset_n(reset_n), // Active-low reset
// CMOS Output Interface (400MHz Domain)
.clk_400m_cmos(clk_400m) // ADC data clock (CMOS, 3.3V)
);
// NOTE: lvds_to_cmos_400m removed — ad9484_interface_400m now provides
// the buffered 400MHz DCO clock via adc_dco_bufg, avoiding duplicate
// IBUFDS instantiations on the same LVDS clock pair.
// 1. ADC + CDC + AGC
// CMOS Output Interface (400MHz Domain)
wire [7:0] adc_data_cmos; // 8-bit ADC data (CMOS)
wire adc_dco_cmos; // ADC data clock (CMOS, 400MHz)
wire [7:0] adc_data_cmos; // 8-bit ADC data (CMOS, from ad9484_interface_400m)
wire adc_valid; // Data valid signal
wire [7:0] cdc_data_cmos; // 8-bit ADC data (CMOS)
wire cdc_valid; // Data valid signal
// ADC power-down control (directly tie low = ADC always on)
assign adc_pwdn = 1'b0;
ad9484_lvds_to_cmos_400m adc (
ad9484_interface_400m adc (
.adc_d_p(adc_d_p),
.adc_d_n(adc_d_n),
.adc_dco_p(adc_dco_p),
.adc_dco_n(adc_dco_n),
.sys_clk(clk),
.reset_n(reset_n),
.adc_data_cmos(adc_data_cmos),
.adc_dco_cmos(adc_dco_cmos),
.adc_valid(adc_valid),
.adc_pwdn(adc_pwdn)
.adc_data_400m(adc_data_cmos),
.adc_data_valid_400m(adc_valid),
.adc_dco_bufg(clk_400m)
);
cdc_adc_to_processing #(
.WIDTH(8),
.STAGES(3)
)cdc(
.src_clk(adc_dco_cmos),
.src_clk(clk_400m),
.dst_clk(clk_400m),
.reset_n(reset_n),
.src_data(adc_data_cmos),
@@ -199,7 +193,7 @@ always @(posedge clk or negedge reset_n) begin
if (sample_addr_reg == 1023) sample_addr_reg <= 0;
end
end
assign sample_addr_wire = sample_addr_reg;
// sample_addr_wire removed — was unused implicit wire (synthesis warning)
// 4. CRITICAL: Reference Chirp Latency Buffer
// This aligns reference data with FFT output (2159 cycle delay)
@@ -249,8 +243,6 @@ matched_filter_multi_segment mf_dual (
.segment_request(segment_request),
.mem_request(mem_request),
.sample_addr_out(sample_addr_from_chain),
.ref_i(16'd0), // Direct ref to multi_seg
.ref_q(16'd0),
.mem_ready(mem_ready),
.pc_i_w(range_profile_i),
.pc_q_w(range_profile_q),
@@ -338,7 +330,7 @@ doppler_processor_optimized #(
.doppler_output(doppler_output),
.doppler_valid(doppler_valid),
.doppler_bin(doppler_bin),
.range_bin(doppler_range_bin_out),
.range_bin(range_bin),
// Status
.processing_active(doppler_processing),
@@ -347,9 +339,8 @@ doppler_processor_optimized #(
);
// ========== OUTPUT CONNECTIONS ==========
assign doppler_range_bin = doppler_range_bin_out;
assign doppler_processing_active = doppler_processing;
assign doppler_frame_complete = doppler_frame_done;
// doppler_output, doppler_valid, doppler_bin, range_bin are directly
// connected to doppler_proc ports above
// ========== STATUS ==========
9_Firmware/9_2_FPGA/xfft_32.v
+71
View File
@@ -0,0 +1,71 @@
`timescale 1ns / 1ps
// ============================================================================
// xfft_32.v — Synthesis stub for Xilinx 32-point FFT IP core
// ============================================================================
// This is a PLACEHOLDER module that provides the port interface expected by
// doppler_processor.v. It does NOT perform an actual FFT — it simply passes
// input data through with a one-cycle latency and generates proper AXI-Stream
// handshake signals.
//
// For real hardware, replace this stub with either:
// (a) A Xilinx FFT IP core generated via Vivado IP Catalog, or
// (b) A custom synthesizable radix-2 DIT 32-point FFT in Verilog.
//
// Port interface matches the Xilinx LogiCORE IP Fast Fourier Transform
// (AXI-Stream variant) as instantiated in doppler_processor.v.
// ============================================================================
module xfft_32 (
input wire aclk,
input wire aresetn,
// Configuration channel (AXI-Stream slave)
input wire [7:0] s_axis_config_tdata,
input wire s_axis_config_tvalid,
output wire s_axis_config_tready,
// Data input channel (AXI-Stream slave)
input wire [31:0] s_axis_data_tdata,
input wire s_axis_data_tvalid,
input wire s_axis_data_tlast,
// Data output channel (AXI-Stream master)
output wire [31:0] m_axis_data_tdata,
output wire m_axis_data_tvalid,
output wire m_axis_data_tlast,
input wire m_axis_data_tready
);
// ----------------------------------------------------------------------------
// Synthesis stub: pass-through with one-cycle latency
// ----------------------------------------------------------------------------
// This gives Vivado a real module to synthesize so it can check port
// connectivity, infer timing paths, and estimate utilization. The actual
// FFT computation is deferred to IP integration or a custom RTL FFT.
// ----------------------------------------------------------------------------
// Always accept config
assign s_axis_config_tready = 1'b1;
// Pipeline registers for data pass-through
reg [31:0] data_reg;
reg valid_reg;
reg last_reg;
always @(posedge aclk) begin
if (!aresetn) begin
data_reg <= 32'd0;
valid_reg <= 1'b0;
last_reg <= 1'b0;
end else begin
data_reg <= s_axis_data_tdata;
valid_reg <= s_axis_data_tvalid;
last_reg <= s_axis_data_tlast;
end
end
assign m_axis_data_tdata = data_reg;
assign m_axis_data_tvalid = valid_reg;
assign m_axis_data_tlast = last_reg;
endmodule