Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

Resolves all synthesis errors across attempts 3-11, achieving clean
Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs).

radar_receiver_final.v:
- reg clk_400m -> wire; output reg -> output wire (x4)
- Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m
- Remove duplicate IBUFDS lvds_to_cmos_400m instantiation
- Remove non-existent ref_i/ref_q port connections on matched filter
- Connect adc_dco_bufg as 400MHz clock source

ad9484_interface_400m.v:
- Add adc_dco_bufg output port with BUFG instance
- Route all internal logic through buffered DCO clock

cic_decimator_4x_enhanced.v:
- Move reset_monitors handling inside else branch (fixes Vivado
  ambiguous clock error in both integrator and comb always blocks)
- Add separate comb_overflow_latched/comb_saturation_detected regs
  to eliminate multi-driven nets between integrator and comb blocks
- Remove standalone always @(posedge reset_monitors) block
- Add output_counter to async reset branch

matched_filter_processing_chain.v:
- Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION
- Add synthesis stub tying outputs to safe defaults

chirp_memory_loader_param.v:
- Replace hardcoded Windows paths with relative filenames for all
  10 $readmem default parameters

latency_buffer_2159.v:
- Split single always block into separate BRAM write (synchronous
  only) and control logic (with async reset) blocks
- Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset

xfft_32.v (NEW):
- Synthesis stub for Xilinx 32-point FFT IP core
- AXI-Stream interface with pass-through and 1-cycle latency
- Placeholder until real xfft IP is generated

9_Firmware/9_2_FPGA/xfft_32.v

@@ -0,0 +1,71 @@
+`timescale 1ns / 1ps
+// ============================================================================
+// xfft_32.v — Synthesis stub for Xilinx 32-point FFT IP core
+// ============================================================================
+// This is a PLACEHOLDER module that provides the port interface expected by
+// doppler_processor.v. It does NOT perform an actual FFT — it simply passes
+// input data through with a one-cycle latency and generates proper AXI-Stream
+// handshake signals.
+//
+// For real hardware, replace this stub with either:
+//   (a) A Xilinx FFT IP core generated via Vivado IP Catalog, or
+//   (b) A custom synthesizable radix-2 DIT 32-point FFT in Verilog.
+//
+// Port interface matches the Xilinx LogiCORE IP Fast Fourier Transform
+// (AXI-Stream variant) as instantiated in doppler_processor.v.
+// ============================================================================
+
+module xfft_32 (
+    input  wire        aclk,
+    input  wire        aresetn,
+
+    // Configuration channel (AXI-Stream slave)
+    input  wire [7:0]  s_axis_config_tdata,
+    input  wire        s_axis_config_tvalid,
+    output wire        s_axis_config_tready,
+
+    // Data input channel (AXI-Stream slave)
+    input  wire [31:0] s_axis_data_tdata,
+    input  wire        s_axis_data_tvalid,
+    input  wire        s_axis_data_tlast,
+
+    // Data output channel (AXI-Stream master)
+    output wire [31:0] m_axis_data_tdata,
+    output wire        m_axis_data_tvalid,
+    output wire        m_axis_data_tlast,
+    input  wire        m_axis_data_tready
+);
+
+// ----------------------------------------------------------------------------
+// Synthesis stub: pass-through with one-cycle latency
+// ----------------------------------------------------------------------------
+// This gives Vivado a real module to synthesize so it can check port
+// connectivity, infer timing paths, and estimate utilization. The actual
+// FFT computation is deferred to IP integration or a custom RTL FFT.
+// ----------------------------------------------------------------------------
+
+// Always accept config
+assign s_axis_config_tready = 1'b1;
+
+// Pipeline registers for data pass-through
+reg [31:0] data_reg;
+reg        valid_reg;
+reg        last_reg;
+
+always @(posedge aclk) begin
+    if (!aresetn) begin
+        data_reg  <= 32'd0;
+        valid_reg <= 1'b0;
+        last_reg  <= 1'b0;
+    end else begin
+        data_reg  <= s_axis_data_tdata;
+        valid_reg <= s_axis_data_tvalid;
+        last_reg  <= s_axis_data_tlast;
+    end
+end
+
+assign m_axis_data_tdata  = data_reg;
+assign m_axis_data_tvalid = valid_reg;
+assign m_axis_data_tlast  = last_reg;
+
+endmodule