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Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

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Resolves all synthesis errors across attempts 3-11, achieving clean
Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs).

radar_receiver_final.v:
- reg clk_400m -> wire; output reg -> output wire (x4)
- Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m
- Remove duplicate IBUFDS lvds_to_cmos_400m instantiation
- Remove non-existent ref_i/ref_q port connections on matched filter
- Connect adc_dco_bufg as 400MHz clock source

ad9484_interface_400m.v:
- Add adc_dco_bufg output port with BUFG instance
- Route all internal logic through buffered DCO clock

cic_decimator_4x_enhanced.v:
- Move reset_monitors handling inside else branch (fixes Vivado
  ambiguous clock error in both integrator and comb always blocks)
- Add separate comb_overflow_latched/comb_saturation_detected regs
  to eliminate multi-driven nets between integrator and comb blocks
- Remove standalone always @(posedge reset_monitors) block
- Add output_counter to async reset branch

matched_filter_processing_chain.v:
- Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION
- Add synthesis stub tying outputs to safe defaults

chirp_memory_loader_param.v:
- Replace hardcoded Windows paths with relative filenames for all
  10 $readmem default parameters

latency_buffer_2159.v:
- Split single always block into separate BRAM write (synchronous
  only) and control logic (with async reset) blocks
- Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset

xfft_32.v (NEW):
- Synthesis stub for Xilinx 32-point FFT IP core
- AXI-Stream interface with pass-through and 1-cycle latency
- Placeholder until real xfft IP is generated
This commit is contained in:
Jason
2026-03-15 17:37:59 +02:00
parent c871281f1e
commit eefaf94e9e
7 changed files with 407 additions and 321 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/latency_buffer_2159.v
+60 -57
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@@ -39,63 +39,66 @@ initial begin
buffer_has_data = 0;
end
// ========== FIXED STATE MACHINE ==========
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
write_ptr <= 0;
read_ptr <= 0;
valid_out_reg <= 0;
delay_counter <= 0;
buffer_has_data <= 0;
end else begin
// Default: no valid output
valid_out_reg <= 0;
// ===== WRITE SIDE =====
if (valid_in) begin
// Store data
bram[write_ptr] <= data_in;
// Increment write pointer (wrap at 4095)
if (write_ptr == 4095) begin
write_ptr <= 0;
end else begin
write_ptr <= write_ptr + 1;
end
// Count how many samples we've written
if (delay_counter < LATENCY) begin
delay_counter <= delay_counter + 1;
// When we've written LATENCY samples, buffer is "primed"
if (delay_counter == LATENCY - 1) begin
buffer_has_data <= 1'b1;
// $display("[LAT_BUF] Buffer now has %d samples (primed)", LATENCY);
end
end
end
// ===== READ SIDE =====
// Only start reading after we have LATENCY samples in buffer
if (buffer_has_data && valid_in) begin
// Read pointer follows write pointer with LATENCY delay
// Calculate: read_ptr = (write_ptr - LATENCY) mod 4096
// Handle wrap-around correctly
if (write_ptr >= LATENCY) begin
read_ptr <= write_ptr - LATENCY;
end else begin
// Wrap around: 4096 + write_ptr - LATENCY
read_ptr <= 4096 + write_ptr - LATENCY;
end
// Output is valid
valid_out_reg <= 1'b1;
//$display("[LAT_BUF] Reading: write_ptr=%d, read_ptr=%d, data=%h",
// write_ptr, read_ptr, bram[read_ptr]);
end
end
// ========== BRAM WRITE (synchronous only, no async reset) ==========
// Xilinx Block RAMs do not support asynchronous resets.
// Separating the BRAM write into its own always block avoids Synth 8-3391.
// The initial block above handles power-on initialization for FPGA.
always @(posedge clk) begin
if (valid_in) begin
bram[write_ptr] <= data_in;
end
end
// ========== CONTROL LOGIC (with async reset) ==========
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
write_ptr <= 0;
read_ptr <= 0;
valid_out_reg <= 0;
delay_counter <= 0;
buffer_has_data <= 0;
end else begin
// Default: no valid output
valid_out_reg <= 0;
// ===== WRITE SIDE =====
if (valid_in) begin
// Increment write pointer (wrap at 4095)
if (write_ptr == 4095) begin
write_ptr <= 0;
end else begin
write_ptr <= write_ptr + 1;
end
// Count how many samples we've written
if (delay_counter < LATENCY) begin
delay_counter <= delay_counter + 1;
// When we've written LATENCY samples, buffer is "primed"
if (delay_counter == LATENCY - 1) begin
buffer_has_data <= 1'b1;
end
end
end
// ===== READ SIDE =====
// Only start reading after we have LATENCY samples in buffer
if (buffer_has_data && valid_in) begin
// Read pointer follows write pointer with LATENCY delay
// Calculate: read_ptr = (write_ptr - LATENCY) mod 4096
// Handle wrap-around correctly
if (write_ptr >= LATENCY) begin
read_ptr <= write_ptr - LATENCY;
end else begin
// Wrap around: 4096 + write_ptr - LATENCY
read_ptr <= 4096 + write_ptr - LATENCY;
end
// Output is valid
valid_out_reg <= 1'b1;
end
end
end
// ========== OUTPUTS ==========