FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache

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FIR: Add coeff_reg/mult_reg pipeline stages to fix 68 DPIP-1 + 35 DPOP-2
DRC warnings. Valid pipeline widened 7→9 bits (+2 cycle latency).

Matched filter: Migrate input_buffer_i/q from register arrays to BRAM
(~33K FF savings). Overlap-save uses register cache captured during
ST_PROCESSING to avoid BRAM read/write conflicts during overlap copy.
New ST_OVERLAP_COPY state writes cached tail samples back sequentially.

Both changes pass 18/18 FPGA regression. Golden data regenerated for
+2 FIR latency baseline.

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This commit is contained in:

Jason

2026-03-19 20:39:01 +02:00

parent 4e3c20066b

commit ed6f79c6d3

5 changed files with 4538 additions and 4395 deletions

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9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv

+2048 -2048

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