FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache

FIR: Add coeff_reg/mult_reg pipeline stages to fix 68 DPIP-1 + 35 DPOP-2
DRC warnings. Valid pipeline widened 7→9 bits (+2 cycle latency).

Matched filter: Migrate input_buffer_i/q from register arrays to BRAM
(~33K FF savings). Overlap-save uses register cache captured during
ST_PROCESSING to avoid BRAM read/write conflicts during overlap copy.
New ST_OVERLAP_COPY state writes cached tail samples back sequentially.

Both changes pass 18/18 FPGA regression. Golden data regenerated for
+2 FIR latency baseline.

9_Firmware/9_2_FPGA/tb/tb_fir_lowpass.v

@@ -109,8 +109,8 @@ module tb_fir_lowpass;
         saw_nonzero = 0;
         output_count = 0;
 
-        // Run for 40 clocks (need at least 32 for all taps + pipeline)
-        for (sample_count = 0; sample_count < 40; sample_count = sample_count + 1) begin
+        // Run for 44 clocks (need at least 32 for all taps + 9-stage pipeline)
+        for (sample_count = 0; sample_count < 44; sample_count = sample_count + 1) begin
             @(posedge clk); #1;
             if (data_out_valid) begin
                 $fwrite(csv_file, "%0d,%0d\n", output_count, data_out);