feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

Complete cross-layer upgrade from 1024-pt/64-bin to 2048-pt/512-bin FFT:

FPGA RTL (14+ modules):
- radar_params.vh: FFT_SIZE=2048, RANGE_BINS=512, 9-bit range, 6-bit stream
- fft_engine.v: 2048-pt FFT with XPM BRAM
- chirp_memory_loader_param.v: 2 segments x 2048 (was 4 x 1024)
- matched_filter_multi_segment.v: BRAM inference for overlap_cache, explicit ov_waddr
- mti_canceller.v: BRAM inference for prev_i/q arrays (was fabric FFs)
- doppler_processor.v: 16384-deep memory, 14-bit addressing
- cfar_ca.v: 512 rows, indentation fix
- radar_receiver_final.v: rising-edge detector for frame_complete, 11-bit sample_addr
- range_bin_decimator.v: 512 output bins
- usb_data_interface_ft2232h.v: bulk per-frame with Manhattan magnitude
- radar_mode_controller.v: XOR edge detector for toggle signals
- rx_gain_control.v: updated for new bin count

Python GUI + Protocol (8 files):
- radar_protocol.py: 512-bin bulk frame parser, LSB-first bitmap
- GUI_V65_Tk.py, v7/*.py: updated for 512 bins, 6m range resolution

Golden data + tests:
- All .hex/.csv/.npy golden references regenerated for 2048/512
- fft_twiddle_2048.mem added
- Deleted stale seg2/seg3 chirp mem files
- 9 new bulk frame cross-layer tests, deleted 6 stale per-sample tests
- Deleted stale tb_cross_layer_ft2232h.v and dead contract_parser functions
- Updated validate_mem_files.py for 2048/2-segment config

MCU: RadarSettings.cpp max_distance/map_size 1536->3072

All 4 CI jobs pass: 285 tests, 0 failures, 0 skips

9_Firmware/9_2_FPGA/run_regression.sh

@@ -381,6 +381,13 @@ run_doppler_cosim() {
 #   run_test <name> <vvp_path> <iverilog_args...>
 # ---------------------------------------------------------------------------
 run_test() {
+    # Optional: --timeout=N as first arg overrides default 120s
+    local timeout_secs=120
+    if [[ "$1" == --timeout=* ]]; then
+        timeout_secs="${1#--timeout=}"
+        shift
+    fi
+
     local name="$1"
     local vvp="$2"
     shift 2
@@ -398,7 +405,7 @@ run_test() {
 
     # Run
     local output
-    output=$(timeout 120 vvp "$vvp" 2>&1) || true
+    output=$(timeout "$timeout_secs" vvp "$vvp" 2>&1) || true
 
     # Count PASS/FAIL in output (testbenches use explicit [PASS]/[FAIL] markers)
     local test_pass test_fail
@@ -548,6 +555,23 @@ if [[ "$QUICK" -eq 0 ]]; then
     # A proper full-pipeline co-sim (DDC→MF→Decim→Doppler vs Python) is
     # planned as a replacement (Phase C of CI test plan).
 
+    # Receiver integration (structural + bounds + pulse assertions)
+    # Tests the full RX pipeline: ADC stub → DDC → MF → Decim → Doppler
+    # Verifies doppler_frame_done is a single-cycle pulse (catches
+    # level-vs-pulse wiring bugs at module boundaries).
+    run_test --timeout=600 "Receiver Integration (tb_radar_receiver_final)" \
+        tb/tb_rx_final_reg.vvp \
+        tb/tb_radar_receiver_final.v \
+        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
+        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        rx_gain_control.v \
+        chirp_memory_loader_param.v latency_buffer.v \
+        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        range_bin_decimator.v mti_canceller.v \
+        doppler_processor.v xfft_16.v fft_engine.v \
+        radar_mode_controller.v
+
     # Full system top (monitoring-only, legacy)
     run_test "System Top (radar_system_tb)" \
         tb/tb_system_reg.vvp \