From e8b7cb75845b32fa13bf5b27cff2e972b237344b Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Thu, 19 Mar 2026 20:53:29 +0200
Subject: [PATCH] Fix matched filter synth errors: overlap_copy_count
 part-select width, add FSM default

Vivado 2025.2 (Synth 8-524): overlap_copy_count is 8-bit but [9:0]
part-select was 10-bit. Changed to explicit zero-extend concat.
Added default case to FSM to suppress non-full case warning.
---
 9_Firmware/9_2_FPGA/matched_filter_multi_segment.v | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/9_Firmware/9_2_FPGA/matched_filter_multi_segment.v b/9_Firmware/9_2_FPGA/matched_filter_multi_segment.v
index fae6b94..720545d 100644
--- a/9_Firmware/9_2_FPGA/matched_filter_multi_segment.v
+++ b/9_Firmware/9_2_FPGA/matched_filter_multi_segment.v
@@ -454,7 +454,7 @@ always @(posedge clk or negedge reset_n) begin
             ST_OVERLAP_COPY: begin
                 // Write one cached overlap sample per cycle to BRAM
                 buf_we <= 1;
-                buf_waddr <= overlap_copy_count[9:0];
+                buf_waddr <= {{2{1'b0}}, overlap_copy_count};
                 buf_wdata_i <= overlap_cache_i[overlap_copy_count];
                 buf_wdata_q <= overlap_cache_q[overlap_copy_count];
                 
@@ -476,6 +476,10 @@ always @(posedge clk or negedge reset_n) begin
                     end
                 end
             end
+            
+            default: begin
+                state <= ST_IDLE;
+            end
         endcase
         
         // Update status