feat: CI test suite phases A+B, WaveformConfig separation, dead golden code cleanup
- Phase A: Remove self-blessing golden test from FPGA regression, wire MF co-sim (4 scenarios) into run_regression.sh, add opcode count guards to cross-layer tests (+3 tests) - Phase B: Add radar_params.vh parser and architectural param consistency tests (+7 tests), add banned stale-value pattern scanner (+1 test) - Separate WaveformConfig.range_resolution_m (physical, bandwidth-dependent) from bin_spacing_m (sample-rate dependent); rename all callers - Remove 151 lines of dead golden generate/compare code from tb_radar_receiver_final.v; testbench now runs structural + bounds only - Untrack generated MF co-sim CSV files, gitignore tb/golden/ directory CI: 256 tests total (168 python + 40 cross-layer + 27 FPGA + 21 MCU), all green
This commit is contained in:
Jason
@@ -253,6 +253,68 @@ run_lint_static() {
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fi
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}
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# ---------------------------------------------------------------------------
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# Helper: compile, run, and compare a matched-filter co-sim scenario
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# run_mf_cosim <scenario_name> <define_flag>
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# ---------------------------------------------------------------------------
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run_mf_cosim() {
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local name="$1"
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local define="$2"
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local vvp="tb/tb_mf_cosim_${name}.vvp"
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local scenario_lower="$name"
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printf " %-45s " "MF Co-Sim ($name)"
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# Compile — build command as string to handle optional define
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local cmd="iverilog -g2001 -DSIMULATION"
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if [[ -n "$define" ]]; then
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cmd="$cmd $define"
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fi
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cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v chirp_memory_loader_param.v"
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if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
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echo -e "${RED}COMPILE FAIL${NC}"
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ERRORS="$ERRORS\n MF Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
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FAIL=$((FAIL + 1))
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return
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fi
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# Run TB
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local output
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output=$(timeout 120 vvp "$vvp" 2>&1) || true
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rm -f "$vvp"
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# Check TB internal pass/fail
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local tb_fail
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tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
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if [[ "$tb_fail" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} (TB internal failure)"
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ERRORS="$ERRORS\n MF Co-Sim ($name): TB internal failure"
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FAIL=$((FAIL + 1))
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return
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fi
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# Run Python compare
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if command -v python3 >/dev/null 2>&1; then
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local compare_out
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local compare_rc=0
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compare_out=$(python3 tb/cosim/compare_mf.py "$scenario_lower" 2>&1) || compare_rc=$?
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if [[ "$compare_rc" -ne 0 ]]; then
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echo -e "${RED}FAIL${NC} (compare_mf.py mismatch)"
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ERRORS="$ERRORS\n MF Co-Sim ($name): Python compare failed"
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FAIL=$((FAIL + 1))
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return
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fi
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else
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echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
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SKIP=$((SKIP + 1))
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return
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fi
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echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
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PASS=$((PASS + 1))
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}
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# ---------------------------------------------------------------------------
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# Helper: compile and run a single testbench
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# run_test <name> <vvp_path> <iverilog_args...>
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@@ -416,30 +478,14 @@ run_test "Full-Chain Real-Data (decim→Doppler, exact match)" \
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doppler_processor.v xfft_16.v fft_engine.v
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if [[ "$QUICK" -eq 0 ]]; then
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# Golden generate
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run_test "Receiver (golden generate)" \
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tb/tb_rx_golden_reg.vvp \
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-DGOLDEN_GENERATE \
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tb/tb_radar_receiver_final.v radar_receiver_final.v \
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radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
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cdc_modules.v fir_lowpass.v ddc_input_interface.v \
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chirp_memory_loader_param.v latency_buffer.v \
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matched_filter_multi_segment.v matched_filter_processing_chain.v \
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range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
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rx_gain_control.v mti_canceller.v
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# Golden compare
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run_test "Receiver (golden compare)" \
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tb/tb_rx_compare_reg.vvp \
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tb/tb_radar_receiver_final.v radar_receiver_final.v \
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radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
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cdc_modules.v fir_lowpass.v ddc_input_interface.v \
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chirp_memory_loader_param.v latency_buffer.v \
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matched_filter_multi_segment.v matched_filter_processing_chain.v \
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range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
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rx_gain_control.v mti_canceller.v
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# NOTE: The "Receiver golden generate/compare" pair was REMOVED because
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# it was self-blessing: both passes ran the same RTL with the same
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# deterministic stimulus, so the test always passed regardless of bugs.
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# Real co-sim coverage is provided by:
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# - tb_doppler_realdata.v (committed Python golden hex, exact match)
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# - tb_fullchain_realdata.v (committed Python golden hex, exact match)
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# A proper full-pipeline co-sim (DDC→MF→Decim→Doppler vs Python) is
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# planned as a replacement (Phase C of CI test plan).
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# Full system top (monitoring-only, legacy)
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run_test "System Top (radar_system_tb)" \
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@@ -469,12 +515,28 @@ if [[ "$QUICK" -eq 0 ]]; then
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usb_data_interface.v edge_detector.v radar_mode_controller.v \
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rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
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else
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echo " (skipped receiver golden + system top + E2E — use without --quick)"
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SKIP=$((SKIP + 4))
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echo " (skipped system top + E2E — use without --quick)"
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SKIP=$((SKIP + 2))
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fi
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echo ""
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# ===========================================================================
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# PHASE 2b: MATCHED FILTER CO-SIMULATION (RTL vs Python golden reference)
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# Runs tb_mf_cosim.v for 4 scenarios, then compare_mf.py validates output
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# against committed Python golden CSV files. In SIMULATION mode, thresholds
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# are generous (behavioral vs fixed-point twiddles differ) — validates
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# state machine mechanics, output count, and energy sanity.
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# ===========================================================================
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echo "--- PHASE 2b: Matched Filter Co-Sim ---"
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run_mf_cosim "chirp" ""
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run_mf_cosim "dc" "-DSCENARIO_DC"
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run_mf_cosim "impulse" "-DSCENARIO_IMPULSE"
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run_mf_cosim "tone5" "-DSCENARIO_TONE5"
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echo ""
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# ===========================================================================
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# PHASE 3: UNIT TESTS — Signal Processing
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# ===========================================================================
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