Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)
RTL fix: matched_filter_multi_segment.v ST_WAIT_FFT now waits for processing chain to complete ALL 1024 outputs and return to IDLE before advancing to next segment. Previously, it transitioned on the first fft_pc_valid edge, causing the chain to still be outputting while multi-seg started collecting data for the next segment. This broke the handshake and caused permanent deadlock after segment 0. Also fixes forward reference of sample_addr_from_chain in radar_receiver_final.v (declaration moved before first use). New files: - tb/tb_radar_receiver_final.v: P0 integration test for full RX pipeline (ADC->DDC->MF->range_bin_decimator->doppler), 10 checks - tb/ad9484_interface_400m_stub.v: behavioral ADC stub for iverilog All existing tests still pass: multi-seg 32/32, MF co-sim 3/3, Doppler co-sim 14/14.
This commit is contained in:
Jason
@@ -0,0 +1,53 @@
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`timescale 1ns / 1ps
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// ============================================================================
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// ad9484_interface_400m_stub.v -- Behavioral stub for iverilog simulation
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//
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// Replaces the real ad9484_interface_400m which uses Xilinx primitives
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// (IBUFDS, BUFG, IDDR) that cannot compile in iverilog.
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//
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// Convention for testbench use:
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// - Drive adc_d_p[7:0] with single-ended 8-bit ADC data
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// - Drive adc_dco_p with the 400MHz clock (testbench-generated)
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// - adc_d_n and adc_dco_n are ignored
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// - adc_dco_bufg = adc_dco_p (pass-through, no BUFG)
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// - 1-cycle pipeline latency on data, same as real IDDR+register path
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// ============================================================================
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module ad9484_interface_400m (
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// ADC Physical Interface (LVDS)
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input wire [7:0] adc_d_p,
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input wire [7:0] adc_d_n,
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input wire adc_dco_p,
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input wire adc_dco_n,
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// System Interface
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input wire sys_clk,
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input wire reset_n,
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// Output at 400MHz domain
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output wire [7:0] adc_data_400m,
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output wire adc_data_valid_400m,
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output wire adc_dco_bufg
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);
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// Pass-through clock (no BUFG needed in simulation)
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assign adc_dco_bufg = adc_dco_p;
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// 1-cycle pipeline register (matches real IDDR + output register latency)
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reg [7:0] adc_data_400m_reg;
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reg adc_data_valid_400m_reg;
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always @(posedge adc_dco_p or negedge reset_n) begin
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if (!reset_n) begin
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adc_data_400m_reg <= 8'b0;
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adc_data_valid_400m_reg <= 1'b0;
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end else begin
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adc_data_400m_reg <= adc_d_p;
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adc_data_valid_400m_reg <= 1'b1;
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end
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end
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assign adc_data_400m = adc_data_400m_reg;
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assign adc_data_valid_400m = adc_data_valid_400m_reg;
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endmodule
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,444 @@
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`timescale 1ns / 1ps
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// ============================================================================
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// tb_radar_receiver_final.v -- P0 Integration Test for radar_receiver_final
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//
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// Tests the full RX pipeline from ADC input to Doppler output:
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// ad9484_interface (stub) -> CDC -> DDC -> ddc_input_interface
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// -> matched_filter_multi_segment -> range_bin_decimator
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// -> doppler_processor_optimized -> doppler_output
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//
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// Strategy:
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// - Uses behavioral stub for ad9484_interface_400m (no Xilinx primitives)
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// - Overrides radar_mode_controller timing params for fast simulation
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// - Feeds 120 MHz tone at ADC input (IF frequency -> DDC passband)
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// - Verifies structural correctness of Doppler outputs:
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// * Outputs appear (doppler_valid asserted)
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// * Correct output count per frame (64 range bins x 32 Doppler bins = 2048)
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// * Range bin index covers 0..63
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// * Doppler bin index covers 0..31
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// * Output values are non-trivial (not all zeros)
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// - Does NOT require bit-perfect match (too many cascaded stages)
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//
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// Convention: check task, VCD dump, CSV output, pass/fail summary
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// ============================================================================
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module tb_radar_receiver_final;
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// ============================================================================
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// CLOCK AND RESET
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// ============================================================================
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reg clk_100m; // 100 MHz system clock
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reg clk_400m; // 400 MHz ADC clock
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reg reset_n;
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// 100 MHz: period = 10 ns
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initial clk_100m = 0;
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always #5 clk_100m = ~clk_100m;
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// 400 MHz: period = 2.5 ns
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initial clk_400m = 0;
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always #1.25 clk_400m = ~clk_400m;
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// ============================================================================
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// ADC STIMULUS
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// ============================================================================
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// Feed a 120 MHz tone (IF frequency) sampled at 400 MHz
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// Phase increment per sample: 120/400 * 65536 = 19660.8
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// This produces a strong DC component after DDC downconversion
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reg [7:0] adc_data;
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reg [15:0] phase_acc; // 16-bit phase accumulator for precision
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localparam [15:0] PHASE_INC = 16'd19661; // 120/400 * 65536
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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phase_acc <= 16'd0;
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adc_data <= 8'd128; // Mid-scale
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end else begin
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phase_acc <= phase_acc + PHASE_INC;
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// Use phase_acc[15:8] directly as pseudo-sinusoidal data
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// A sawtooth/triangle wave has energy at IF -- good enough for integration test
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adc_data <= phase_acc[15:8];
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end
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end
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// ============================================================================
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// CHIRP COUNTER (external input to DUT)
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// ============================================================================
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// In the real system, this comes from the transmitter. For the test,
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// we increment it on each mc_new_chirp toggle from the mode controller.
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// Access the internal signal via hierarchical reference.
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reg [5:0] chirp_counter;
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reg mc_new_chirp_prev;
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always @(posedge clk_100m or negedge reset_n) begin
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if (!reset_n) begin
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chirp_counter <= 6'd0;
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mc_new_chirp_prev <= 1'b0;
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end else begin
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mc_new_chirp_prev <= dut.mc_new_chirp;
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if (dut.mc_new_chirp != mc_new_chirp_prev) begin
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chirp_counter <= chirp_counter + 1;
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end
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end
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end
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// ============================================================================
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// DUT INSTANTIATION
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// ============================================================================
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wire [31:0] doppler_output;
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wire doppler_valid;
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wire [4:0] doppler_bin;
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wire [5:0] range_bin_out;
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radar_receiver_final dut (
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.clk(clk_100m),
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.reset_n(reset_n),
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// ADC "LVDS" -- stub treats adc_d_p as single-ended data
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.adc_d_p(adc_data),
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.adc_d_n(~adc_data), // Complement (ignored by stub)
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.adc_dco_p(clk_400m), // 400 MHz clock
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.adc_dco_n(~clk_400m), // Complement (ignored by stub)
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.adc_pwdn(),
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.chirp_counter(chirp_counter),
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.doppler_output(doppler_output),
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.doppler_valid(doppler_valid),
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.doppler_bin(doppler_bin),
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.range_bin(range_bin_out)
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);
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// ============================================================================
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// OVERRIDE TIMING PARAMETERS via defparam
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// ============================================================================
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// Reduce radar_mode_controller timing to keep simulation tractable.
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// Real values: LONG_CHIRP=3000, LONG_LISTEN=13700, GUARD=17540,
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// SHORT_CHIRP=50, SHORT_LISTEN=17450 (total ~51740 per chirp)
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// Need enough DDC samples to fill MF buffer (896) plus latency buffer (3187).
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// At ~1 DDC sample per sys_clk, we need at least ~5000 sys_clk per chirp.
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// Use moderately reduced values: ~5000 cycles per chirp pair
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defparam dut.rmc.LONG_CHIRP_CYCLES = 500;
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defparam dut.rmc.LONG_LISTEN_CYCLES = 2000;
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defparam dut.rmc.GUARD_CYCLES = 500;
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defparam dut.rmc.SHORT_CHIRP_CYCLES = 50;
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defparam dut.rmc.SHORT_LISTEN_CYCLES = 1000;
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// ============================================================================
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// TEST INFRASTRUCTURE
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// ============================================================================
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integer pass_count;
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integer fail_count;
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integer total_tests;
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task check;
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input cond;
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input [512*8-1:0] label;
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begin
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total_tests = total_tests + 1;
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if (cond) begin
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pass_count = pass_count + 1;
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$display("[PASS %0d] %0s", total_tests, label);
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end else begin
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fail_count = fail_count + 1;
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$display("[FAIL %0d] %0s", total_tests, label);
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end
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end
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endtask
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// ============================================================================
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// OUTPUT MONITORING
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// ============================================================================
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integer doppler_output_count;
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integer doppler_frame_count;
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reg [63:0] range_bin_seen; // Bitmap: which range bins appeared
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reg [31:0] doppler_bin_seen; // Bitmap: which Doppler bins appeared
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integer nonzero_output_count;
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reg [31:0] first_doppler_time; // Cycle when first doppler_valid appears
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reg first_doppler_seen;
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// Per-frame tracking
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integer frame_output_count;
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reg frame_done_prev;
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// CSV output
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integer csv_fd;
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initial begin
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doppler_output_count = 0;
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doppler_frame_count = 0;
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range_bin_seen = 64'd0;
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doppler_bin_seen = 32'd0;
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nonzero_output_count = 0;
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first_doppler_seen = 0;
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first_doppler_time = 0;
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frame_output_count = 0;
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frame_done_prev = 0;
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csv_fd = $fopen("tb/cosim/rx_final_doppler_out.csv", "w");
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if (csv_fd) $fdisplay(csv_fd, "cycle,range_bin,doppler_bin,output_hex");
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end
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// Monitor doppler outputs -- only after reset released
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always @(posedge clk_100m) begin
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if (reset_n && doppler_valid) begin
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doppler_output_count = doppler_output_count + 1;
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frame_output_count = frame_output_count + 1;
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// Track which bins we've seen
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if (range_bin_out < 64)
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range_bin_seen = range_bin_seen | (64'd1 << range_bin_out);
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if (doppler_bin < 32)
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doppler_bin_seen = doppler_bin_seen | (32'd1 << doppler_bin);
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// Track non-zero outputs
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if (doppler_output != 32'd0)
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nonzero_output_count = nonzero_output_count + 1;
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// Record first output time
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if (!first_doppler_seen) begin
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first_doppler_seen = 1;
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first_doppler_time = $time;
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$display("[INFO] First doppler_valid at time %0t", $time);
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end
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// CSV logging
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if (csv_fd)
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$fdisplay(csv_fd, "%0t,%0d,%0d,%08h", $time, range_bin_out, doppler_bin, doppler_output);
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// Progress reporting (every 256 outputs)
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if ((doppler_output_count % 256) == 0)
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$display("[INFO] %0d doppler outputs so far (t=%0t)", doppler_output_count, $time);
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end
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// Track frame completions via doppler_proc -- only after reset
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if (reset_n && dut.doppler_frame_done && !frame_done_prev) begin
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doppler_frame_count = doppler_frame_count + 1;
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$display("[INFO] Doppler frame %0d complete: %0d outputs (t=%0t)",
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doppler_frame_count, frame_output_count, $time);
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frame_output_count = 0;
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end
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frame_done_prev = dut.doppler_frame_done;
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end
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// ============================================================================
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// PROGRESS MONITOR -- pipeline stage activity
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// ============================================================================
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reg [31:0] ddc_valid_count;
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reg [31:0] mf_valid_count;
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reg [31:0] range_decim_count;
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reg [31:0] range_data_valid_count;
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initial begin
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ddc_valid_count = 0;
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mf_valid_count = 0;
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range_decim_count = 0;
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range_data_valid_count = 0;
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end
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always @(posedge clk_100m) begin
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if (dut.adc_valid_sync) ddc_valid_count = ddc_valid_count + 1;
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if (dut.range_valid) mf_valid_count = mf_valid_count + 1;
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if (dut.decimated_range_valid) range_decim_count = range_decim_count + 1;
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if (dut.range_data_valid) range_data_valid_count = range_data_valid_count + 1;
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end
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// Periodic progress dump
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reg [31:0] progress_timer;
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initial progress_timer = 0;
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always @(posedge clk_100m) begin
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progress_timer = progress_timer + 1;
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if (progress_timer % 50000 == 0) begin
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$display("[PROGRESS t=%0t] ddc_valid=%0d mf_out=%0d range_decim=%0d doppler_out=%0d chirp=%0d",
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$time, ddc_valid_count, mf_valid_count, range_decim_count,
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doppler_output_count, chirp_counter);
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end
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end
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// ============================================================================
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// MF PIPELINE DEBUG MONITOR — track state transitions
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// ============================================================================
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reg [3:0] mf_state_prev;
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reg [3:0] chain_state_prev;
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initial begin
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mf_state_prev = 0;
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chain_state_prev = 0;
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end
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always @(posedge clk_100m) begin
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// Multi-segment FSM state changes
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if (dut.mf_dual.state != mf_state_prev) begin
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$display("[MF_DBG t=%0t] multi_seg state: %0d -> %0d (seg=%0d, wr_ptr=%0d, rd_ptr=%0d, samples=%0d)",
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$time, mf_state_prev, dut.mf_dual.state,
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dut.mf_dual.current_segment, dut.mf_dual.buffer_write_ptr,
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dut.mf_dual.buffer_read_ptr, dut.mf_dual.chirp_samples_collected);
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mf_state_prev = dut.mf_dual.state;
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end
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// Processing chain state changes
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if (dut.mf_dual.m_f_p_c.state != chain_state_prev) begin
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$display("[CHAIN_DBG t=%0t] chain state: %0d -> %0d (fwd_count=%0d, out_count=%0d)",
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$time, chain_state_prev, dut.mf_dual.m_f_p_c.state,
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dut.mf_dual.m_f_p_c.fwd_in_count, dut.mf_dual.m_f_p_c.out_count);
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chain_state_prev = dut.mf_dual.m_f_p_c.state;
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end
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// Watch for fft_pc_valid while multi-seg is in ST_WAIT_FFT
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if (dut.mf_dual.state == 5 && dut.mf_dual.fft_pc_valid) begin
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$display("[MF_DBG t=%0t] *** fft_pc_valid=1 while in ST_WAIT_FFT! Should transition!", $time);
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end
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// Watch for fft_pc_valid while multi-seg is NOT in ST_WAIT_FFT
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if (dut.mf_dual.state != 5 && dut.mf_dual.fft_pc_valid) begin
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$display("[MF_DBG t=%0t] WARNING: fft_pc_valid=1 but multi_seg state=%0d (NOT ST_WAIT_FFT)",
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$time, dut.mf_dual.state);
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end
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end
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// ============================================================================
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// MAIN TEST SEQUENCE
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// ============================================================================
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// Simulation timeout calculation:
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// 1. DDC pipeline fill: ~4 sys_clk cycles
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// 2. MF overlap-save buffer fill: 896 valid DDC samples
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// 3. Latency buffer priming: 3187 valid_in assertions
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// 4. 1024 MF outputs -> range_bin_decimator -> 64 decimated outputs
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// 5. 32 chirps of decimated data -> Doppler FFT
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//
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// With shortened mode controller timing (~600 cycles per chirp pair),
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// DDC output rate depends on how many 400MHz samples per chirp period
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// produce valid 100MHz outputs (CIC 4x decimation = ~1 per 4 clk_400m).
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//
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// Conservative estimate: ~500K 100MHz cycles for the full pipeline.
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// ~4050 cycles/chirp x 32 chirps = ~130K, plus latency buffer priming,
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// plus Doppler processing time. Set generous timeout.
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localparam SIM_TIMEOUT = 2_000_000; // 2M cycles — full pipeline with multi-segment drain
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initial begin
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// VCD dump disabled for long integration test -- uncomment for debug
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// $dumpfile("tb/tb_radar_receiver_final.vcd");
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// $dumpvars(0, tb_radar_receiver_final);
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pass_count = 0;
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fail_count = 0;
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total_tests = 0;
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// ---- RESET ----
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reset_n = 0;
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#100;
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reset_n = 1;
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$display("[INFO] Reset released at t=%0t", $time);
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// ---- WAIT FOR PIPELINE ----
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// Poll until first Doppler frame completes or timeout
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begin : wait_loop
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integer wait_cycles;
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wait_cycles = 0;
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while (doppler_frame_count < 1 && wait_cycles < SIM_TIMEOUT) begin
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@(posedge clk_100m);
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wait_cycles = wait_cycles + 1;
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end
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if (doppler_frame_count >= 1) begin
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$display("[INFO] First Doppler frame completed at t=%0t", $time);
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#1000;
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end else begin
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$display("[WARN] Simulation timeout reached at t=%0t (%0d cycles)", $time, wait_cycles);
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$display("[WARN] Pipeline progress: ddc_valid=%0d mf_out=%0d range_decim=%0d doppler=%0d",
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ddc_valid_count, mf_valid_count, range_decim_count, doppler_output_count);
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end
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end
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// ---- RUN CHECKS ----
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$display("");
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$display("============================================================");
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$display("RADAR RECEIVER FINAL -- INTEGRATION TEST RESULTS");
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$display("============================================================");
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$display("Total doppler outputs: %0d", doppler_output_count);
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$display("Doppler frames complete: %0d", doppler_frame_count);
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$display("Non-zero outputs: %0d", nonzero_output_count);
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$display("DDC valid count: %0d", ddc_valid_count);
|
||||
$display("MF output count: %0d", mf_valid_count);
|
||||
$display("Range decim count: %0d", range_decim_count);
|
||||
$display("============================================================");
|
||||
$display("");
|
||||
|
||||
// ---- CHECK 1: Pipeline activity ----
|
||||
check(ddc_valid_count > 0,
|
||||
"DDC produces valid outputs (adc_valid_sync asserted)");
|
||||
|
||||
// ---- CHECK 2: MF outputs appear ----
|
||||
check(mf_valid_count > 0,
|
||||
"Matched filter produces outputs (range_valid asserted)");
|
||||
|
||||
// ---- CHECK 3: Range decimator outputs appear ----
|
||||
check(range_decim_count > 0,
|
||||
"Range bin decimator produces outputs");
|
||||
|
||||
// ---- CHECK 4: Doppler outputs appear ----
|
||||
check(doppler_output_count > 0,
|
||||
"Doppler processor produces outputs (doppler_valid asserted)");
|
||||
|
||||
// ---- CHECK 5: Correct output count per frame ----
|
||||
// A complete Doppler frame should produce 64 x 32 = 2048 outputs
|
||||
if (doppler_frame_count > 0) begin
|
||||
check(doppler_output_count >= 2048,
|
||||
"At least 2048 doppler outputs (one full frame: 64 rbins x 32 dbins)");
|
||||
end else begin
|
||||
check(0, "At least 2048 doppler outputs (NO FRAME COMPLETED)");
|
||||
end
|
||||
|
||||
// ---- CHECK 6: Range bin coverage ----
|
||||
// Count how many unique range bins appeared
|
||||
begin : count_range_bins
|
||||
integer rb_count, rb_i;
|
||||
rb_count = 0;
|
||||
for (rb_i = 0; rb_i < 64; rb_i = rb_i + 1) begin
|
||||
if (range_bin_seen[rb_i]) rb_count = rb_count + 1;
|
||||
end
|
||||
$display("[INFO] Unique range bins seen: %0d / 64", rb_count);
|
||||
check(rb_count == 64,
|
||||
"All 64 range bins present in Doppler output");
|
||||
end
|
||||
|
||||
// ---- CHECK 7: Doppler bin coverage ----
|
||||
begin : count_doppler_bins
|
||||
integer db_count, db_i;
|
||||
db_count = 0;
|
||||
for (db_i = 0; db_i < 32; db_i = db_i + 1) begin
|
||||
if (doppler_bin_seen[db_i]) db_count = db_count + 1;
|
||||
end
|
||||
$display("[INFO] Unique Doppler bins seen: %0d / 32", db_count);
|
||||
check(db_count == 32,
|
||||
"All 32 Doppler bins present in Doppler output");
|
||||
end
|
||||
|
||||
// ---- CHECK 8: Non-trivial outputs ----
|
||||
check(nonzero_output_count > 0,
|
||||
"At least some Doppler outputs are non-zero");
|
||||
|
||||
// ---- CHECK 9: Non-zero fraction ----
|
||||
// With a tone input, we expect most outputs to have some energy
|
||||
if (doppler_output_count > 0) begin
|
||||
check(nonzero_output_count > doppler_output_count / 4,
|
||||
"More than 25pct of Doppler outputs are non-zero");
|
||||
end else begin
|
||||
check(0, "More than 25pct of Doppler outputs are non-zero (NO OUTPUTS)");
|
||||
end
|
||||
|
||||
// ---- CHECK 10: Pipeline didn't stall ----
|
||||
check(ddc_valid_count > 100,
|
||||
"DDC produced substantial output (>100 valid samples)");
|
||||
|
||||
// ---- SUMMARY ----
|
||||
$display("");
|
||||
$display("============================================================");
|
||||
$display("SUMMARY: %0d / %0d tests passed", pass_count, total_tests);
|
||||
if (fail_count == 0)
|
||||
$display("ALL TESTS PASSED");
|
||||
else
|
||||
$display("SOME TESTS FAILED (%0d failures)", fail_count);
|
||||
$display("============================================================");
|
||||
|
||||
if (csv_fd) $fclose(csv_fd);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user