Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)

RTL fix: matched_filter_multi_segment.v ST_WAIT_FFT now waits for
processing chain to complete ALL 1024 outputs and return to IDLE
before advancing to next segment. Previously, it transitioned on the
first fft_pc_valid edge, causing the chain to still be outputting
while multi-seg started collecting data for the next segment. This
broke the handshake and caused permanent deadlock after segment 0.

Also fixes forward reference of sample_addr_from_chain in
radar_receiver_final.v (declaration moved before first use).

New files:
- tb/tb_radar_receiver_final.v: P0 integration test for full RX
  pipeline (ADC->DDC->MF->range_bin_decimator->doppler), 10 checks
- tb/ad9484_interface_400m_stub.v: behavioral ADC stub for iverilog

All existing tests still pass: multi-seg 32/32, MF co-sim 3/3,
Doppler co-sim 14/14.

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -170,6 +170,7 @@ ddc_input_interface ddc_if (
 );
 
 // 3. Dual Chirp Memory Loader
+wire [9:0] sample_addr_from_chain;
 
 chirp_memory_loader_param chirp_mem (
     .clk(clk),
@@ -219,7 +220,6 @@ assign short_chirp_real = delayed_ref_i;
 assign short_chirp_imag = delayed_ref_q;
 
 // 5. Dual Chirp Matched Filter
-wire [9:0] sample_addr_from_chain; 
 
 wire signed [15:0] range_profile_i;
 wire signed [15:0] range_profile_q;