Tracked Timing Baseline
-WNS +0.058 ns
-WHS +0.068, WPWS +0.684 after validated Build 16 XDC port
-Open-Source Phased Array Radar
-Engineering Documentation Site
-This site tracks architecture, validated implementation baselines, constraint cleanup progress, and pre-hardware bring-up readiness for AERIS-10.
- +AERIS-10 Open Source
Phased Array Radar
+ A low-cost, hackable 10.5 GHz phased array radar system with Pulse LFM modulation. Designed for researchers, drone developers, and serious SDR enthusiasts.
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+ 🔓 Open Source
+ 📡 10.5 GHz
+ 🎯 3km / 20km Range
+ 🔄 Electronic Beam Steering
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Regression Status
-MCU 15 / 15, FPGA 18 / 18
-Host firmware regression plus FPGA unit and integration suites passing
-Methodology State
-XDCB-5 = 0
-Single documented TIMING-18 residue on `ft601_txe` async observation
-Current Phase
-Pre-Hardware Readiness
-Board-arrival smoke test, artifact inventory, and open-risk tracking prepared
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- Project Overview
+Democratizing radar technology through open-source hardware and software
+What changed recently
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- Ported the validated Build 16 production-target XDC cleanup into the tracked repository. -
- Preserved positive post-route timing while clearing XDCB-5 and reducing methodology residue to a single documented item. -
- Validated the tracked branch with MCU host regression and FPGA regression/integration suites. -
- Refreshed the bring-up documentation into a pre-arrival readiness package for the FPGA module and carrier board. -
- Kept upstream ADAR1000 bulk imports out of the baseline pending selective, justified reuse only. -
Documentation Map
- -AERIS-10 Radar System
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- Alpha prototype hardware
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+ Technical Specifications
+Two versions available to match your range requirements
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+ | Specification | +AERIS-10N (Nexus) | +AERIS-10X (Extended) | +
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| Frequency | 10.5 GHz | 10.5 GHz |
| Max Range | 3 km | 20 km |
| Antenna Type | 8×16 Patch Array | 32×16 Slotted Waveguide |
| Beam Steering | Electronic (±45°) | Electronic (±45°) |
| Mechanical Scan | 360° (stepper motor) | 360° (stepper motor) |
| Output Power | ~1W | 10W (GaN amplifier) |
| Processing | FPGA + STM32 | FPGA + STM32 |
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+ System Architecture
+Modular design with specialized components for optimal performance
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+ +┌─────────────────────────────────────────────────────────────┐ +│ Antenna Array │ +│ (8x16 patch / 32x16 slotted waveguide) │ +└─────────────────────┬───────────────────────────────────────┘ + │ +┌─────────────────────┴───────────────────────────────────────┐ +│ Main Board │ +│ ┌───────────────┐ ┌──────────────┐ ┌─────────────────┐ │ +│ │ XC7A100T │ │ STM32F746 │ │ 16x ADTR1107 │ │ +│ │ FPGA │ │ MCU │ │ Front End │ │ +│ └───────────────┘ └──────────────┘ └─────────────────┘ │ +│ ┌───────────────┐ ┌──────────────┐ ┌─────────────────┐ │ +│ │ 4x ADAR1000 │ │ 2x ADF4382 │ │ 2x LT5552 │ │ +│ │ Phase Shift │ │ Synthesizers│ │ Mixers │ │ +│ └───────────────┘ └──────────────┘ └─────────────────┘ │ +└─────────────────────┬───────────────────────────────────────┘ + │ +┌─────────────────────┴───────────────────────────────────────┐ +│ Support Modules │ +│ ┌───────────────┐ ┌──────────────┐ ┌─────────────────┐ │ +│ │ AD9523-1 │ │ GPS Module │ │ GY-85 IMU │ │ +│ │ Clock Gen │ │ │ │ │ │ +│ └───────────────┘ └──────────────┘ └─────────────────┘ │ +└─────────────────────────────────────────────────────────────┘ ++
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+ 📡 Power Management Board
+Supplies all necessary voltage levels with proper filtering and sequencing (controlled by microcontroller).
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+ ⏱️ Frequency Synthesizer Board
+High-performance AD9523-1 low jitter clock generator with phase-aligned references for RX/TX, DAC, ADC, and FPGA.
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+ 🔄 Main Board Components
+DAC for chirp generation, LT5552 mixers, ADAR1000 phase shifters (4x), ADTR1107 front-end chips (16x).
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+ 🎛️ XC7A100T FPGA
+Handles PLFM chirp generation, ADC data read, AGC, I/Q down-conversion, decimation, filtering, FFT, pulse compression, Doppler, MTI & CFAR processing.
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+ ⚙️ STM32F746 Microcontroller
+Power sequencing, FPGA communication, peripheral configuration (clock generator, synthesizers, phase shifters, GPS, IMU, barometer, stepper motor, sensors).
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+ 🔊 Power Amplifier Boards (10X only)
+10W QPA2962 GaN amplifier for extended range capability.
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+ Current Status
+Alpha prototype - Actively seeking contributors and beta testers
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+ ✅ Working Features
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- Beam formation from 16×8 array +
- Electronic steering ±45° elevation +
- Pulse LFM generation and reception +
- Basic target detection to 1km +
- Full FPGA processing pipeline +
- Pulse compression & Doppler processing +
- MTI & CFAR detection +
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+ 🚧 In Progress
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- Python GUI-based radar processing +
- Multi-board synchronization +
- Extended range testing +
- Crowdfunding campaign +
- Documentation & assembly guides +
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+ Get Involved
+Join the open-source radar revolution
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+ 🤝 We're Actively Seeking
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📬 Connect With Us
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+ Documentation
+Everything you need to build, modify, and operate the AERIS-10 radar
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+ 📘 Hardware Design Guide
+Schematics, PCB layouts, BOM, and assembly instructions.
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+ 💾 Firmware Development
+STM32 firmware and FPGA bitstream programming guide.
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+ 🔬 Signal Processing
+Detailed explanation of the FPGA processing pipeline.
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+ 🐍 Python SDK
+GUI and API reference for data visualization and control.
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+ ⚙️ Calibration Guide
+Step-by-step calibration procedures for optimal performance.
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+ 🛠️ Troubleshooting
+Common issues and solutions.
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