fix: use authoritative tx frame signal for frame sync, consistent ad9523 error path

FPGA-001: The previous fix derived frame boundaries from chirp_counter==0,
but that counter comes from plfm_chirp_controller_enhanced which overflows
to N (not wrapping at chirps_per_elev). This caused frame pulses only on
6-bit rollover (every 64 chirps) instead of every N chirps. Now wires the
CDC-synchronized tx_new_chirp_frame_sync signal from the transmitter into
radar_receiver_final, giving correct per-frame timing for any N.

STM32-004: Changed ad9523_init() failure path from Error_Handler() to
return -1, matching the pattern used by ad9523_setup() and ad9523_status()
in the same function. Both halt the system, but return -1 keeps IRQs
enabled for diagnostic output.

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -505,6 +505,8 @@ radar_receiver_final rx_inst (
     
     // Chirp counter from transmitter (CDC-synchronized from 120 MHz domain)
     .chirp_counter(tx_current_chirp_sync),
+    // Frame-start pulse from transmitter (CDC-synchronized toggle→pulse)
+    .tx_frame_start(tx_new_chirp_frame_sync),
     
     // ADC Physical Interface
     .adc_d_p(adc_d_p),